Development of Keil compiler constructs for an ARM-based embedded application - Embedded.com

Development of Keil compiler constructs for an ARM-based embedded application

Embedded systems are evolving around us into various products. Every 18 months the transistor density increases as per Moore’s law and we able to have better features of the peripherals within the microcontroller.

When a computer architecture had been built it needs to support the compiler constructs to support the higher language constructs. Compiler developers are a team of people who understands the architecture to build the efficient compilers. But it is too hard to have compilers which satisfy all the features of the architecture.

Cutting down the time to market for products that became more and more complex is possible through “re-use”. Another important characteristics of the embedded system market is the ease of incorporating late design changes, i.e. flexibility of the target technology, this led to the use of processors in embedded systems. This in turn led to the use of embedded software.

Over the past 15 years, the ARM reduced instruction set computing (RISC) processor has evolved to offer a family of chips that range up to a full-blown multiprocessor. Embedded applications demand for increasing levels of performance and the added efficiency of key new technologies have driven the ARM architecture’s evolution.

This paper is an implementation of a compiler using Keil tool for an ARM7TDMI-S microprocessor for an embedded application which will reduce the code size to approximately 5% of a code which has already passed through all the levels of optimization embedded in the Keil compiler. A compiler is said to be retargetable, if it can be applied to a range of different target processors, by re-using most of the code. This means that target model cannot be an implicit part, but must be specified explicitly.

The Systems Architecture Laboratory designed and implemented the first phase C programming language compiler for the ARM7TDMI architecture. It consists of two parts: analysis and synthesis. The optimized code produced by the compiler after passing through nine levels of optimization could be reduced further.

Simulation has shown that a further reduction of approximately 5% could be achieved by using this algorithm. The proposed algorithm will be tested for Thumb instructions also which already reduces 30% of the code when compared to ARM.

Used is a compiler in Visual Basic capable of generating MIPS and ARM code. This compiler is a user retargetable compiler. The retargetable efforts are intermediate. Some of the information is entered as parameters through the graphical user interface and rest is used at the time of coding. The following can be provided to the CPU: size of the register file, name of registers and details of functional units. It is observed that the code is good in terms of code size, cycle count and compilation times.

To read more of this external content, download the complete paper from the author archives at IJAREEIE.

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