DisplayPort ESD and CDE protection for version 1.1a compliance - Embedded.com

DisplayPort ESD and CDE protection for version 1.1a compliance

DisplayPort is a new graphics communications interface that seeks to do for the PC what HDMI did for the TV — display HD video content. And as with HDMI, there are unique protection issues with DisplayPort designs, stemming from the high-speed of the interface and the constant threat of electro static and cable discharge events from normal use.

The DisplayPort standard is an uncompressed, open digital communication interface that represents a cost reduction opportunity for PC makers by consolidating the internal and external interconnect. When used internally, it is an interface within a PC or monitor. Externally, it connects a PC to a monitor or projector, or TV. When used as an external interface, the DisplayPort plug is frequently exposed to electrostatic discharge (ESD) directly from the user or cable discharge (CDE) from hot plug cable.

To ensure proper functionality, DisplayPort-based systems must protect all potentially exposed interface signals and power pins to meet or exceed the EOS (electrical over stress) specification of IEC 61000-4-2, Level 4 (+/- 15kV Air, +/-8kV Contact) without damage.

In most cases, the on-chip ESD protection is no longer sufficient to meet this EOS requirement, making off chip ESD protection circuitry necessary for EOS compliance. Providing this protection is further complicated by the high-speed of the link rates; both 2.7Gbps and 1.62Gbps are supported in the standard. At such a high data rate, signal integrity and impedance requirements are given more focus than ever before, as put forth in the DisplayPort Compliant Test Specification (CTS).

Note: A more detailed description of the DisplayPort standard appears on the last page.

The ESD/CDE landscape:
Increasing ESD/CDE events, decreasing on-chip protection

Interface ESD protection has become increasingly difficult as the industry moves along its current process technology trajectory. Simultaneous demands for faster processing speed and higher functional density have resulted in further shrinkage of the minimum dimensions of MOS devices. In early 2007, Intel introduced its first processor prototypes based on a 45-nanometer technology. However, as IC chips grow smaller, denser, and more complex, they become more susceptible to ESD events.

On-chip ESD shunting structures were traditionally employed to protect the inner circuitry from ESD strikes; yet, they are increasingly sacrificed in favor of performance as the geometries continue to shrink making chip real estate more valuable.

In August 2007, the Industry Council on ESD Target Levels released a proposal to lower on-chip IC ESD target levels from 2kV HBM (Human Body Model) / 200V MM (Machine Model) to 1kV HBM / 30V MM to facilitate the industry's ability to design and quickly bring to market high-speed and high-performance ICs. In the meantime, the system level ESD target levels remain at 8kV contact / 15kV air discharge as put forth in IEC 61000-4-2. Therefore, while carefully designed on-chip ESD structures may still serve as excellent secondary protection, sufficient standards-compliant protection can only be realized with robust off-chip solutions.

Another reason why off-chip protection is necessary and important has a lot to do with the placement of the protection element. Normally the on-chip protection circuitry resides too far away from the interface entry point. When ESD-induced transients travel, they can be coupled into nearby traces including data lines, clock signal lines, and power lines. What is more, the magnitude of their voltage is increased due to the Ldi/dt effect (Vpk=Vesd + Ldi/dt).

Cable discharge
I/O applications — like DisplayPort — are subject to another common type of ESD known as cable discharge (CDE). It occurs when a charged cable is plugged into its receptacle and the difference in the potential causes a sudden discharge into the circuit that can cause damage to the IC. Simply pulling a cable out of its packing can make it charged, not to mention dragging it along the carpet to accumulate more charges. There is not yet an established CDE standard, but significant efforts have been made to address this both on the system level and component level. Currently, the common practice in the industry is to test the system per IEC standard.

Next: Human Body Model (HBM), Machines Model (MM) and Charged Device Model (CDM)
What does the ESD rating mean?
Component level vs. system level stress model

Before discussing the specific needs of DisplayPort designs, it's important to know the differences between the various ESD ratings. There are three basic models of ESD: Human Body Model (HBM), Machines Model (MM) and Charged Device Model (CDM). The HBM is further divided into system-level testing and component-level testing, covered by IEC 61000-4-2 and MIL-STD-883 respectively. Both standards are widely accepted in the industry for ESD compliance. Unfortunately, these two standards can be, at times, misunderstood and misquoted in technical literature.


Figure 1: ESD Human Body Model

Component-level HBM is intended to ensure safe manufacturing of the IC in an ESD-controlled manufacturing environment. System-level ESD levels, on the other hand, are more useful for the system designer because they indicate the amount of system-level protection that the device provides. There is no strict correlation between component level ESD robustness and system-level ESD robustness.

A chip protected to 2kV HBM does not mean it will protect a system to survive a 2kV discharge per IEC 61000-4-2. Figure 1 is the general ESD Human Body Model. At component level, the 2kV discharges through a 1.5kΩresistor per MIL-STD-883, Method 3015, rendering a peak current of approximately 1.33A. However, at the system level, IEC 61000-4-2 is divided into four levels of threat, 2kV, 4kV, 6kV, and 8kV; the threat level 2kV corresponds to a peak current of 7.5A. In reality, most of today's systems are designed to level 4, where the peak current is 30A (Table 1 ), about 22 times the current higher than what the chip is designed to withstand. Therefore, to achieve high system level ESD protection, the system level HBM IEC 61000-4-2 should be followed.

Will a DisplayPort design survive an ESD/CDE event?
Clamping voltage and response time

In early January 2008, VESA released DisplayPort standard Version 1.1a. ESD protection is covered in section 3.5.4 which specified the different ESD requirements for DisplayPort based system and DisplayPort components. According to the standard: “The DisplayPort based system must protect all potentially exposed interface signals and power pins to meet or exceed the EOS (electrical over stress) specification of IEC 61000-4-2, Level 4 (8kV contact) without damage. All signal and power pins of associated DisplayPort components (transmitter IC, receiver IC, and associated I/O circuitry) must also withstand at least JEDEC JESD22-A114-B Class 2 (2kV Human Body Model, 200V Machine Model) strikes.”

IEC 61000-4-2
A device rated at IEC 61000-4-2 does not guarantee the system will pass ESD testing. The purpose of a protection device is to reduce an 8kV IEC 61000-4-2 contact input down to a safe voltage for the protected IC. Clamping voltage, by definition, is the maximum voltage drop across the protection device during an ESD event, which is also the stress voltage seen by the protected IC. The ideal protection device should remain invisible during normal operation; turn on immediately in an event of ESD strike and limit the voltage across the protected devices to a level just above the normal operating voltage and well below the destructive threshold. This is particularly important in a DisplayPort application, because DisplayPort devices are required to limit their swing of the I/O lines within +/-0.3V single-ended with respect to the common mode bias reference level, which sits at 2V maximum .

The current industry practice is to publish clamping voltages based on a pulse with an 8uS rise time and a 20uS duration. Most datasheets will publish their clamping voltage using a 1A pulse or sometimes a higher current pulse. Sometimes, a graph of clamping voltage versus peak current is presented too. It is very good data to use to compare the clamping performance of the device, however it has nothing to do with the very fast ESD pulse defined in IEC61000-4-2. A screenshot of the voltage waveform over a device under an ESD pulse input best demonstrates the clamping characteristics of the device. The lower the clamping voltage is, the lower the voltage level is on the protected IC. Therefore, the system is more likely to survive an ESD event.


Table 1: IEC 61000-4-2 Severity Levels and Test Voltages

When comparing the clamping performance of two devices, the parts must be targeted at equivalent applications, with similar package size, capacitance range and working voltage. As the device data rate continuously increases to 1Gbps and beyond, 2.7Gbps in the case of DisplayPort, ESD protection become more challenging. The ESD protection devices have to remain small so as to conserve board space, in the meantime, the capacitance and clamping voltage need to be as low as possible so it won't corrupt the signals.

Next: Response Time, TVS Diodes
Response Time
ESD is a very fast transient pulse. IEC 61000-4-2 models the rise time at 700ps to 1 ns, with a duration of 60ns (Figure 2 ).

Figure 2: ESD Waveform per IEC 61000-4-2

This means the protection circuit needs to turn on very quickly in response to an IEC 61000-4-2 pulse so as to protect the system. Hence response time is an important factor when choosing ESD protection devices.

TVS diodes
The preferred ESD protection solution is TVS (Transient Voltage Suppressor) diodes. TVS diodes are specially engineered diodes.


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Figure 3: Semtech's RoHS Compliant SLP Packages (inconclusive)

They are small (Figure 3 , Semtech's RoHS Compliant SLP packages), have low capacitance (Figure 4 , typical capacitance of 0.3pF line to line) and leakage current, respond quickly in an event of ESD, and most importantly, have very low clamping voltage, and do not degrade after repeated surges.


Figure 4: Normalized Capacitance vs. Reverse Voltage (RClamp0524P)

A typical ESD response of TVS diode to +8kV contact discharge per IEC 61000-4-2 is shown in Figure 5 . Within nanoseconds, the TVS clamps the 8kV to 13V, safeguarding the protected IC.


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Figure 5: ESD response of TVS diode to +8kV contact discharge per IEC 61000-4-2

Next: Eye Pattern Specifications, Impedance and DisplayPort Compliant Test Specification
Does the system still have an open eye?
Signal integrity and CTS

To ensure interoperability between DisplayPort products, all devices must comply with the requirements set forth in the DisplayPort Compliant Test Specification (CTS).


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Figure 6: EYE Mask at Source Connector Pins (Source: DisplayPort Standard V1.1a)

In DisplayPort applications, high-speed audio/video streams are transmitted over four differential data pairs; there is no dedicated clock signal pair, the clock is embedded in the data stream using 8B/10B coding. The DisplayPort CTS requires that the transmitter meet an eye mask specification in Figure 6 .


Table 2: Mask Vertices for High Bit Rate (2.7 Gbps)

Table 2 shows the vertices for the 2.7Gbps bit rate and Table 3 shows the vertices for the reduced bit rate of 1.62Gbps.


Table 3: Mask Vertices for Reduced Bit Rate (1.62 Gbps)

Impedance and CTS
Protection devices can impact the high-speed signal both electrically and mechanically. These effects are discontinuities due to an impedance change or mismatch on the balanced differential pairs and will result in signal degradation.

The DisplayPort CTS requires the cable and connectors to meet a stringent impedance profile — 100 Ohms +/- 10% for fixture, connector, wire management; 100 Ohms +/-5% for cable. The impedance profile must be measured using a controlled impedance fixture and Time Domain Reflectometry (TDR). The fixture rise time must be 50 ps (20% – 80%) or faster while the readout of measurement must be filtered to tr = 130 ps (20% – 80%).

Imperfections cause added inductance and capacitance load on the high speed differential. As the rise time becomes faster, these impedance mismatches can induce a much more severe impact on the differential impedance, and in turn cause signal degradation to show up as failures in eye diagram testing when an eye mask is applied. Therefore, even though the aforementioned impedance requirements are not mandatory for the source and sink devices, it is recommended.

Next: Capacitive Loading
Capacitive Loading
The capacitive load of ESD protection devices can cause undesirable bumps and dips in the differential impedance, which translate into failures in TDR measurements. PCB board layout methods have been employed to compensate for the capacitive load introduced by an effective ESD protection device for some time. Semtech RClamp0524P emerges as industry's first ESD solution providing reliable ESD protection in excess of IEC 61000-4-2 Level 4, without the need for capacitive compensation. It has a typical capacitance of 0.3pF between I/O pins which has minimum electrical effects on the high speed signal lines and allows it to be used on circuits operating in excess of 3GHz without signal degradation. From a mechanical point of view, the RClamp0524P is housed in a SLP2510P8 package that is specifically designed to reduce its effects on the high speed signal lines. Its unique flow through design (Figure 7 ) allows the traces to run straight through the device and allows the designer to make minimum changes to the layout.


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Figure 7: Flow-through layout of Semtech's RClamp0524P

The unique combination of small size, ultra low capacitance, and high level ESD protection makes RClamp0524P a superior solution to protect the DisplayPort running up to 2.7Gbps.


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Figure 8: DisplayPort EYE Mask Testing Result (Protected by RClamp0524P@1.62Gbps)

Figure 8 and Figure 9 show the eye diagram testing results of a DisplayPort protected by RClamp0524P at 2.7Gbps and 1.62Gbps, respectively. Clearly, the eye mask is not violated in both cases.


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Figure 9: DisplayPort EYE Mask Testing Result (Protected by RClamp0524P @2.7Gbps)

Next: The DisplayPort Standard
What is DisplayPort?
In May 2005, the Video Electronics Standards Association (VESA) announced the development of a new digital interface specification –DisplayPort. Companies backing the standard include Dell, HP, Genesis Microchip, Samsung, NXP, Intel, AMD/ATI, NVIDIA, Molex, and Tyco. In May 2006, VESA announced approval of the DisplayPort 1.0 specification. In March 2007, DisplayPort 1.1 was published; and as of January 11, 2008, version 1.1a was made available to the public.

The DisplayPort standard defines an open digital communication interface for use in both internal connections, such as interfaces within a PC or monitor, and external display connections, including interfaces between a PC and monitor or projector, between a PC and TV, or between a device such as a DVD player and TV display.


Figure 10: DisplayPort Data Transport Channels

The DisplayPort link consists of a uni-directional main link, a bi-directional auxiliary channel, and a hot-plug detect signal line (Figure 10 ). Each main link comprises one, two or four AC-coupled, doubly terminated differential pairs (lanes) with no dedicated clock signal, which is embedded in the 8B/10B coded data stream. AC coupling enables the DisplayPort transmitters and receivers to be fabricated on different processes and hence operate under different common voltages.

Two link rates, 2.7Gbps and 1.62Gbps, are supported. The link rate is decoupled from the pixel rate and the number of lanes is decoupled from the pixel bit depth and component bit depth, which means tradeoffs can easily be made among pixel depth, resolution, frame rate, and the amount of additional information such as audio and HDCP (High-bandwidth Digital Content Protection).

For example, at four lanes, you can either implement a 12 bit/pixel, 4:4:4 YCrCb video stream of 1920×1080 pixel progressive scan resolution @ 96 frames/sec; or a 10 bit RGB video stream of 2560×1536 @ 60 frames/sec. The separate bidirectional auxiliary channel with 1Mbps bandwidth and 500m sec maximum latency handles link management and device control.

About the author
Grace H. Yang is a Product Marketing Engineer in the Protection Products Division of Semtech Corp. In this capacity she coordinates with Field and Factory Applications Engineers, Marketing Communications and other Marketing personnel to define new products, evaluate new markets and create sales tools to support revenue growth. She is responsible for the Digital Video/Computer market segment. Prior to Semtech, she was an ATE consultant at Berkeley Consulting Services Inc. and had been responsible for projects at Agilent/Verigy, nVIDIA, Intersil, Symwave and Wisair etc. She received her MSEE from Auburn University and BSEE from Fudan University (Shanghai, China). She can be reached at .

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