DSP Tricks: DC Removal - Embedded.com

DSP Tricks: DC Removal

When we digitize analog signals using an analog-to-digital (A/D)converter, the converter's output typically contains some small DCbias: that is, the average of the digitized time samples is not zero.That DC bias may have come from theoriginal analog signal or from imperfections within the A/D converter.

Another source of DC bias contamination in digital signal processingis when we truncate a discrete sequence from a B-bit representation toword widths less than B bits. Whatever the source, unwanted DC bias ona signal can cause problems.

When we're performing spectrum analysis, any DC bias on the signalshows up in the frequency domain as energy at zero Hz, the X(0)spectral sample. For an N-point Fast Fourier Transform (FFT) the X(0) spectral value is proportional to Nand becomes inconveniently large for large-sized FFTs.

When we plot our spectral magnitudes, the plotting software willaccommodate any large X(0) value and squash down the remainder of thespectrum in which we are more interested.

A non-zero DC bias level in audio signals is particularlytroublesome because concatenating two audio signals, or switchingbetween two audio signals, results in unpleasant audible clicks. Inmodern digital communications systems, a DC bias on quadrature signalsdegrades system performance and increases bit error rates.

With that said, it's clear that methods for DC removal are ofinterest to many DSP practitioners.

Block-Data DC Removal
If you're processing in non-real-time, and the signal data is acquiredin blocks (fixed-length sequences )of block length N, DC removal is straightforward. We merely compute theaverage of our N time samples, and subtract that average value fromeach original sample to yield a new time sequence whose DC bias will beextremely small.

This scheme, although very effective, is not compatible withcontinuous throughput (real-time) systems. For real-time systems we'reforced to use filters for DC removal.

Real-Time DC Removal
The author has encountered three proposed filters for DC removal shownin Figure 13-62(a), (b) , and (c) below . Ignoring the constantgains of those DC-removal filters, all three filters have identicalperformance with the general DC-removal filter structure in Figure 13-62(d) having a z-domaintransfer function of

It's not immediately obvious that the filters in Figure 13-62(c) and(d) are equivalent. You can verify that equivalency by writing thetime-domain difference equations relating the various nodes in thefeedback path of Figure 13-62(c)'s filter. Next, convert thoseequations to z-transform expressions and solve for Y(z)/X(z) to yieldEq. (13-118)) above.

Figure13″62. Filters used for DC bias removal.

Because the DC-removal filters can be modeled with the general DCremoval filter in Figure 13-62(d), we provide the general filter'sfrequency magnitude and phase responses in Figure 13-63(a) and (b) for α = 0.95 below .

The filter's pole/zero locations are given in Figure 13-63(c), wherea zero resides at z = 1 providing infinite attenuation at DC (zero Hz)and a pole at z = α making the magnitude notch at DC very sharp. Thecloser a is to unity, the narrower the frequency magnitude notchcentered at zero Hz. Figure 13-63(d) shows the general filter'sunit-sample impulse response.

Figure13-63. DC-removal filter, α = 0.95: (a) magnitude response; (b) phaseresponse; (c) pole/zero locations; (d) impulse response.

Figure 13-64 below shows thetime-domain input/output performance of the general DC-removal filter(with α = 0.95) when its input is a sinusoid suddenly contaminated witha DC bias of 2 beginning at the 100th time sample and disappearing atthe 200th sample. The DC-removal filter works well.

Figure13-64. DC-removal filter performance: (a) filter input with sudden DCbias; (b) filter output.

Real-Time DC Removal withQuantization
Because the general DC-removal filter has feedback the y(n) outputsamples may require wider binary word widths than those used for thex(n) input samples. This could result in overflows in fixed-pointbinary implementations. The scaling factors of (1+α)/2 and K, in Figure13-62(a) and (b), are less than one to minimize the chance of y(n)binary overflow.

In fixed-point hardware the y(n) samples are often truncated to thesame word width as the input x(n). This quantization (by means oftruncation) will induce a negative DC bias onto the quantized outputsamples, degrading our desired DC removal.

When we truncate a binary sample value, by discarding some of itsleast significant bits, we induce a negative error in the truncatedsample.

Fortunately, that error value is available for us to add to the nextunquantized signal sample, increasing its positive DC bias. When thatnext sample is truncated, the positive error we've added minimizes thenegative error induced by truncation of the next sample.

Figure 13-65(a) below showsthe addition of a quantizing sigma-delta modulator to the feedback pathof the DC-removal filter given in Figure 13-62(c). The positive errorinduced by truncation quantization (the Q block) is delayed by onesample time and fed back to the quantizer input.

Figure13-65 Two DC-removal filters using fixed-point quantization to avoiddata overflow.

Because the modulator has a noise shaping property wherequantization error noise is shifted up in frequency, away from zero Hz(DC), the overall DC bias at the output of the filter is minimized. Anequivalent quantization noise shaping process can be applied to aDirect Form I version of the Figure 13-62(d) general DC-removal filteras shown in Figure 13-65(b).

Again, the positive quantization error is delayed by one sample timeand added to the quantizer input. To reiterate, the DC-removal filtersin Figure 13-65 are used to avoid binary data overflow, by means ofquantization, without the use of scaling multipliers.

Usedwith the permission of the publisher, Prentice Hall, this on-goingseries of articles on Embedded.com is based on copyrighted materialfrom “UnderstandingDigital Signal Processing, Second Edition” by Richard G. Lyons. Thebook can be purchased on line.

Richard Lyons is a consultingsystems engineer and lecturer with Besser Associates. As alecturer with Besser and an instructor for the University of CaliforniaSanta Cruz Extension, Lyons has delivered digitasl signal processingseminars and training course at technical conferences as well atcompanies such as Motorola, Freescale, Lockheed Martin, TexasInstruments, Conexant, Northrop Grumman, Lucent, Nokia, Qualcomm,Honeywell, National Semiconductor, General Dynamics and Infinion.

1 thought on “DSP Tricks: DC Removal

  1. “You mention that the DC offset increases with the number of samples N? Why is this the case? I would be very appreciative if you could explain it, or perhaps point me towards a resources that does.”

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