DSPs bolster MCUs for wireless designs - Embedded.com

DSPs bolster MCUs for wireless designs

There is a predicable rhythm to microcontroller and processor-based SoC product introductions in those segments of the electronics market focused on consumer wireless, video, and mobile PC/laptop designs. It starts in early fall shortly after original equipment manufacturers have rolled out their designs for the Christmas market, all based on technologies demonstrated by IC makers at the previous January Consumer Electronics Show (CES). This is followed by chip vendors who are already rolling out new components and designs they want to show off at the next CES, where they hope to get enough attention from OEMs to end up in products for the following year’s next Christmas market.

It’s now fall, and based on what chip vendors are talking to me about, my guess is that next year's big consumer designs will center around applications requiring more powerful digital signal processing capabilities. The first to roll out such ICs and processors include companies such as Ensilica, Flex Logix, Microchip and Synopsys.

Synopsys makes a DSP bid with ARC EM9D/11D
The most recent and most impressive rollout so far out is the Synopsys DesignWare ARC EM9D and EM11D processor cores. They have a DSP enhanced version of the ARCv2DSP instruction set architecture (ISA) and have added an X-Y memory system to boost digital signal processing performance while minimizing power consumption.

“We've designed our new cores for a range of IoT applications in the consumer wireless and wearable IoT space, where we expect vendors will be need a lot of DSP capabilities but within very constrained power budgets,” said Angela Raucher, Product Line Manager, ARC EM Processors.

To accomplish that, all of the new EM DSP cores incorporate a three- rather than -five-stage pipeline to achieve lower power consumption. But to make up for possible loss of performance, the new architecture makes use of separate X and Y memory blocks. This allows a system to more closely track and more efficiently process regular data access patterns common in signal processing code. “This architecture is most useful for DSP applications needing fast memory accesses while performing repeated mathematical operations on arrays of numbers,” said Raucher.

Target of chip vendors with DSP add-ons to their microcontrollers and systems on chip is the next generation of wireless wearable IoTs and a range of video and audio related consumer designs.

Target of chip vendors with DSP add-ons to their microcontrollers and systems on chip is the next generation of wireless wearable IoTs and a range of video and audio related consumer designs.

Raucher explained that on-chip address generation units provide additional addressing modes that make complex address calculations independently, removing a significant overhead from the CPU and ensuring efficient memory access without cycle penalties. When used in combination with enhanced direct memory access to more efficiently move data in and out of the block memory, the EM9D/EM11D is able to achieve a sustained throughput of one 32×32 MAC operation or two 16×16 MAC operations per clock cycle with minimal energy and area overhead.

Many new consumer designs will require additional DSP performance to execute complex sensor algorithms, as well as improve processing efficiency for a range of audio formats including MP3, SBC, OPUS and AAC LC. To handle this, the new processor cores support full integer, fractional divide and square root operations, unaligned loads/stores, and bit stream parsing. The result is that when the EM9D is performing MP3 decode at 44.1 kHz and 128 kbps, power consumption is less than 40 microwatts.

Synopsys ARC EM9D and EM11D processor core architecture has added instructions and specialized X-Y memory banks for DSP intensive but low power applications.

Synopsys ARC EM9D and EM11D processor core architecture has added instructions and specialized X-Y memory banks for DSP intensive but low power applications.

The company has also beefed up the tools in its DesignWare ARC Toolkit to make developing DSP apps for consumer designs using XY memory less onerous. For regular C code, the toolkit’s compiler automatically generates the specific ARCv2DSP ISA instructions needed, as well as guided and auto vectorization optimizations. Programmers can efficiently target the cores' DSP and XY memory resources directly through the use of C code with qualifiers and primitives. In addition to a library of new DSP functions such as FFT and DCT, FIR, and IIR filters, as well as vector and matrix math functions, the toolkit includes an ITU-T base-ops library for developing voice codecs.

EnSilica’s eSi-3260 DSP optimized processor core
Impressive as Synopsys’ new cores are, it is not the only company targeting such high performance/low power applications typical of nextgen consumer wearable and IoT applications. For example, EnSilica has just launched its eSi-3260 DSP optimized processor core for use in IoT sensing nodes and always-on applications typical of the consumer market. It incorporates a 64-bit precision, fully-pipelined MAC unit for use in audio, high accuracy sensor hub, motion control, and touch screen applications.

Unlike Synopsys, EnSilica employs a 5-stage pipeline which allows operation at frequencies up to 1GHz with a dynamic power as low as 14µW/MHz. This can be reduced to 3µW/MHz when the core is optimized for lower power. Radix-8 fast divide and square root options enable 32-bit integer division and square root operations to be reduced to six cycles, greatly decreasing the cycle count in sensing designs where these operations are key to efficient code use.

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