Dual-core dsPIC digital signal controller offers design flexibility - Embedded.com

Dual-core dsPIC digital signal controller offers design flexibility

System developers designing high-end embedded control applications can benefit from a new Digital Signal Controller (DSC) with two dsPIC® DSC cores in a single chip, now available from Microchip Technology Inc. The dsPIC33CH has one core that is designed to function as a master while the other is designed as a slave. The slave core is useful for executing dedicated, time-critical control code while the master core is busy running the user interface, system monitoring and communications functions, customized for the end application. The dsPIC33CH is designed specifically to facilitate independent code development for each core by separate design teams and allows seamless integration when they are brought together in one chip.

The dsPIC33CH family is optimized for high-performance digital power, motor control and other applications requiring sophisticated algorithms. This includes applications such as wireless power, server power supplies, drones and automotive sensors. For example, in a digital power supply, the slave core manages the math-intensive algorithms, while the master core independently manages the PMBus™ protocol stack and provides system monitoring functions, increasing overall system performance and responsiveness. Distributing the overall workload across two DSC cores in a single device enables higher power density through higher switching frequencies, leading to smaller components. The dsPIC33CH family was designed for live updating of the system, which is especially important for power supplies where firmware updates must be made with zero downtime.

In an automotive fan or pump, the slave core is dedicated to managing time-critical speed and torque control while the master manages the Controller Area Network Flexible Data rate (CAN-FD) communications, system monitoring and diagnostics. The two cores work seamlessly together, enabling advanced algorithms to improve efficiency and responsiveness. In addition, each of the new cores in the dsPIC33CH devices has been designed to provide more performance than current dsPIC DSC cores through: 1) more context-selected registers to improve interrupt responsiveness; 2) new instructions to accelerate Digital Signal Processor (DSP) performance; and 3) faster instruction execution.

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