Dual-core DVB-S2 demodulator/decoder tailored for FPGA platforms - Embedded.com

Dual-core DVB-S2 demodulator/decoder tailored for FPGA platforms

LONDON — English communications IP vendor Commsonic and French counterpart TurboConcept have released what the two companies claim to be the world's first comprehensive DVB-S2 demodulator/decoder to be tailored for FPGA platforms.

Based around TurboConcept's LDPC decoder and Commsonic's adaptive APSK demodulator, the dual-core 'SkyPlug' solution supports the full range of features provided by the Standard in a scalable package that can accept data rates in excess of 200Mb/s using just two FPGA devices, with a single-device version available by the end of the year.

Recently ratified by ETSI, DVB-S2 is being touted as the long-term replacement for the 10-year-old DVB-S Standard that currently delivers direct-to-home digital TV via satellite to tens of millions of homes around the world.

By using a combination of the latest techniques for linear modulation, synchronisation and FEC, the new standard is able to deliver at least 30% higher capacity in a given block of spectrum than its predecessor and is expected to find mainstream application over the next decade for the distribution of high-definition TV and other broadband services.

Paul Rudkin, Commsonic's marketing director, said, “Until recently we had a situation in which the performance of modern iterative FEC schemes such as Turbo coding and LDPC have exceeded the ability of the demodulator to maintain timing and carrier synchronisation. DVB-S2 has been designed from the ground up to eliminate this mismatch. Our SkyPlug solution can acquire and maintain synchronisation when the signal level is close to half that of the noise.”

In addition to its improved performance and spectrum efficiency, the new Standard features an adaptive coding and modulation (ACM) transmission scheme that allows capacity to be optimised for individual, or groups of, receivers. In the ACM scheme, receivers report their forward link signal-to-noise ratio back to the transmitter which is then able to adjust the modulation and FEC Parameters to suit. This scheme allows a doubling of capacity versus DVB-S and is aimed at non-broadcast and interactive applications, as it can reduce the cost of satellite capacity by a factor of 2 to 2.5 according to some analysts.

SkyPlug is available for both Altera and Xilinx FPGA families and has been verified with Zarlink’s ZL10038 single-chip DVB-S2 Tuner.

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