EDA luminaries join Pulsic advisory board - Embedded.com

EDA luminaries join Pulsic advisory board

LONDON — EDA developer, Pulsic, is setting up a four member advisory board and named Roy E. Jewell, president of Magma Design Automation, and Peter Harverson, former vice president of Cadence Europe, as the first members.

Ken Roberts, chief executive officer, said, “Our goal in forming the advisory board is to bring together a high-level group of advisors with wide-ranging experiences in order to direct and advise us in a variety of ways. We aim to develop an open dialog with our advisors and both Peter and Roy have committed to helping us meet our corporate objectives.”

Roy E. Jewell joined Magma in 2001 as chief operating officer, later assuming the additional role of president. From 1999 to 2001, Jewell served initially as the chief executive officer (CEO) of Clarisay, a company he co-founded and previously worked for Avant!, Technology Modeling Associates, and Texas Instruments.

Peter Harverson has more than 35 years of experience working within the semiconductor and other related industries. Most recently, he held a number of senior executive roles that spanned Europe, Middle East and Africa (EMEA) at Sun Microsystems, including responsibility for its EMEA corporate accounts programs and services sales. Previously he was with Cadence Design Systems, Valid Logic, Dazix, Intel and Texas Instruments. Currently, he is a partner and member of the board with TenSails LLP in Cambridge, England, chairman of Virtual Business Network and a non executive director of Aspex Semiconductor.

The Pulsic (Bristol, England) advisory board will meet quarterly and is designed to draw on the expertise of senior executives who have diverse backgrounds, from marketing and sales to technical and general business experience.

Privately-owned Pulsic was set up in Janaury 2000 and provides advanced physical design solutions for complex analog, custom, digital and mixed-signal IC and SoC designs. Its products include automatic and interactive editing, timing closure solutions, topological routing for power/clock and signal integrity.

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