I love it when competitors play nice with each other, which in the end, is good for everyone in the design community. In this case, I'm referring to a recent announcement made jointly between Cadence Design Systems and Mentor Graphics. The companies are making available their Open Verification Methodology (OVM).
Distributed under the standard open-source Apache 2.0 license, the OVM source code, documentation, and use examples can be downloaded for free from www.ovmworld.org. The OVM Web site is the central point of access for the OVM source code, providing information about partners, events, seminars, training, how-to instructions, and future plans.
The OVM is based on the IEEE Std. 1800-2005 SystemVerilog standard. The companies are calling it the first open, language interoperable, SystemVerilog verification methodology in the industry.
In a nutshell, the OVM provides a methodology and accompanying library that lets designers create modular, reusable verification environments in which components communicate with each other using standard transaction-level modeling interfaces. Just as important, and where the collaboration comes in, it enables intra- and inter-company reuse through a common methodology and classes for virtual sequences and block-to-system reuse, and full integration with other languages commonly used in production flows. The joint development means that the OVM is supported on multiple verification platforms.
Hopefully this is another needed step to help designers stay on the path that continues to get more and more difficult to follow, as system get more and more complex going forward. As always, time will tell.
Richard Nass is editor in chief of Embedded Systems Design magazine. He can be reached at .