eDP: A better embedded display ecosystem - Embedded.com

eDP: A better embedded display ecosystem

Today’s personal electronic devices continue to get smaller and easier to use, with more performance and functionality. Such advances are often driven by technology hidden from the consumer, behind the sleek industrial design and elegant user interface. Video quality improvements are one example. A “better” display is normally equated to more pixels per inch driven by a multi-core GPU that supports high-resolution rendering. But “better” can also be one that uses less power to extend battery life, interferes less with wireless service to enable better coverage, and improves chip integration to enable sleeker, lighter-weight system designs.

These are the types of refinements addressed by the latest revision to the VESA (Video Electronics Standards Association) Embedded DisplayPort Standard. Embedded DisplayPort, commonly known as eDP , is based on the VESA DisplayPort Standard. DisplayPort is the high-performance external audio/visual (A/V) interface developed and deployed by the personal computer industry through collaboration within VESA, providing display resolutions of 4K and beyond. DisplayPort itself continues to gain momentum and is now moving onto tablets and phones as a supporting feature of the new USB-C connector in the form of “DisplayPort Alt Mode.” Like DisplayPort, eDP also offers display resolutions beyond 4K. Designed to replace the internal LVDS display interface developed in the mid 1990s, eDP is used in virtually all new computers with an internal display, including laptops, all-in-ones, and many high-end, higher-resolution tablets.

The development of both DisplayPort and eDP was driven by a variety of computing needs. Foremost among these was hardware integration. As process geometries continued to shrink, a new lower-voltage AC-coupled interface was needed to continue integrating the high-speed display interface into the GPU or system chip. This is because the DC-coupled, high-voltage swing interfaces in use today?including LVDS, DVI, and HDMI?require either the use of external interface chips or process changes that compromise performance. Running at a much higher bit rate, eDP also reduces the number of wires in the interface as well as the number of pins for the interface (Figure 1). The higher bit rate also enables higher resolution, color depth and frame rate. eDP also includes unique features to better manage system power for longer battery life, and lower EMI and RFI thereby reducing the need for heavy and bulky shielding.

click for larger image

Figure 1: At display resolutions beyond Full HD (1920×1080) or Full HD+ (1920×1200), eDP has a significant advantage over LVDS in minimizing the number of high-speed wire pairs needed in the display interface, which in turn results in reduced total system footprint. (Source: VESA)

VESA recently announced an update to the eDP Standard. Called eDP v1.4b, this new version puts the finishing touches on the eDP v1.4 Standard that was released in February 2013. Panels capable of supporting eDP v1.4b are now in production, and eDP v1.4b will be enabled in 2016 notebooks. eDP v1.4b includes several enhancements to enable improved flexibility of system implementation, reduced device complexity and lower bill of materials (BOM) costs. However, before we get into what’s new for eDP v1.4b, let’s look back at why the eDP Standard was first developed, and how it has affected the electronics ecosystem through the collaborative efforts of VESA member companies that continually evolve this standard and propagate it across the supply chain.

Next page >>

Creating the Foundation for eDP
eDP was first introduced in late 2008 as a simplified version of DisplayPort for internal displays. The main goal was a common display interface that could be used for both external and internal displays. Shortly thereafter, the main GPU / CPU vendors, including Intel, NVIDIA and AMD, announced that eDP would replace the current (at that time) LVDS interface standard, and that LVDS support would go away, which it now has. The motivation was simple: The chip industry needed to replace the high-voltage LVDS interface with one that could drive integration and display performance. eDP became the obvious choice because it could repurpose the flexible and extensible DisplayPort interface—meaning the same video port could drive an internal or external display, enabling platform application and design flexibility.

Through subsequent releases of the eDP standard over the last several years, the computer industry OEMs involved with the standard have continued to make refinements unique to eDP and not shared by DisplayPort, at least not at the time. eDP v1.0, which was released in 2008, was basically a simplified version of DisplayPort with a definition of panel power sequencing. In late 2009, eDP v1.1 added system power management enhancements through the introduction of video frame rate control. One of those particular methods later became the Adaptive-Sync feature, now supported by DisplayPort (Figure 2). This was followed by the release of eDP v1.2 in 2010 with a new set of commands sent over the AUX Channel—the sideband bus used for both DisplayPort and eDP—to control other aspects of the display, including backlight brightness and color rendering characteristics. This eliminated the need for other control signals, removing several pins and wires in the display interface. And then in eDP v1.3, published in early 2011, new display protocols were added to enable Panel Self Refresh (PSR), which adds a separate frame buffer to the display and allows the host GPU / CPU to enter a low power state when a static display image is encountered, which is surprisingly often. This feature further reduces power and extends battery life.

click for larger image


click for larger image

Figure 2: Application of Adaptive-Sync to frame rate reduction (A); application of Adaptive-Sync to game rendering (B). (Source: Parade Technologies; galloping-horse photos by Eadweard Muybridge, 1887)

Recent eDP Developments Focused on Power Reduction
Following eDP v1.3, which is commonly used for systems currently in production, eDP v1.4 was introduced in February 2013. eDP v1.4 included many new eDP-specific enhancements targeting further power reduction. One such feature is the partial frame update capability for PSR (PSR2). When the system is displaying a static image in self-refresh mode, such as text, and then just a portion of the image changes, such as the flashing cursor, partial frame update enables the GPU to only send that part of the image instead of the whole video frame (Figure 3). Another important and complementary upgrade is the ability to change the GPU power state more quickly. Enabling the GPU/CPU to quickly exit and enter the low-power state to make a selective image update saves system power.

click for larger image

Figure 3: Comparison between Panel Self Refresh (PSR) and PSR2 (updated version) operation. (Source: Parade Technologies)

eDP v1.4 was also the first video interface standard to leverage a form of display stream compression. This new category of image compression enables the reduction of bit rate and wire count on the video interface, saving power and reducing form factor. It can also be used to reduce the display’s frame buffer size, reducing BOM cost. And eDP v1.4 expanded backlight control to regional backlight control to enable further power savings. Power was also reduced in the high-speed electrical interface that carries the video data. By adding more flexibility in voltage swing and data transport rate, the interface can be better optimized for the system design and display requirements.

Since the publication of eDP v1.4 over two years ago, the PC OEMsworking within VESA have continued to refine the standard and have beenworking toward production beginning in 2016. This led to the publicationof the eDP v1.4a release in early 2015. Two influences for this updatedrelease were the publication of the VESA Display Stream Compression(DSC) Standard v1.0 in March 2014, which was an improvement over thecompression standard used in eDP v1.4, and the publication ofDisplayPort Standard v1.3 in September 2014. Both of these new standardscame after the release of eDP v1.4 in February 2013 and contributedimportant enhancements to eDP v1.4a. For example, the 8.1Gbps link ratedefined in DisplayPort v1.3, coupled with DSC, enables 8K displayresolution support.

eDP v1.4a also added Multi-SST Operation (MSO) to support a segmentedpanel display architecture (Figure 4). This enables a higher level ofintegration on high-resolution displays, allowing integration of thepanel timing controller with source drivers, enabling thinner, lighterdisplays with a lower BOM cost. eDP v1.4a also added Y-coordinates tothe PSR2 partial update command, relaxing time-base accuracyrequirements in the display and thereby eliminating the crystal orcrystal oscillator requirement originally required for an eDP v1.4display – again, further lowering system BOM cost.

click for larger image

Figure4: The eDP v1.4a specification supports Segmented Panel displayarchitectures, which are designed to enable thinner, lighter andlower-cost panels that use less power. (Source: VESA, photo by CraigWiley)

What’s New in eDP 1.4b
With so many new enhancements in eDPv1.4 and eDP v1.4a, OEMs developing the eDP v1.4 products laterdiscovered some vagueness and ambiguities in this committee-generatedstandard, as well as a few conflicts with DisplayPort v1.3. eDP v1.4bbegan as an effort to update the standard with clarifications andcorrections agreed upon within VESA, to promote interoperability amongmember companies, and to minimize time to market. But eDP v1.4b alsoended up incorporating a few other agreed-upon enhancements proposed bysome of the member companies involved.

In particular, the selective update feature for panel self-refreshreceived many refinements and clarifications in protocol. Selectablegranularity for the update region was also added to help reduce thecomplexity of the internal frame buffer storage. Many panel timingcontrollers use image compression, including DSC, for frame bufferstorage. Limiting the X and Y axis granularity of the update regionsimplifies the compression codec implementation and lowers BOM cost.

The AUX Frame Sync requirement was also eliminated for PSR2 ifselective updates are not used, meaning that frame buffer updates aremade a full frame at a time. This eliminates the need to support boththe DisplayPort GTC (Global Time Code) and AUX Frame Sync features,allowing more scalability of the PSR2 function. Cost can be reduced inexchange for a little less power savings. For MSO, additional cyclicredundancy check (CRC) registers were added to enable the verificationof data integrity for the transport of video to each panel segment, upto the four display segments allowed.

Other small adjustments to eDP v1.4b include the removal of a fewcontrol register conflicts with DisplayPort v1.3 and clarification andrefinement of other various protocols and operational sequences. Withthis final cleanup, the VESA members generally agreed that eDP v1.4b isthe final release of the eDP v1.4 standard and that it is ready forproduction.

Made Possible with DisplayPort
The ongoing enhancements toeDP v1.4b have been made possible by the flexible nature of DisplayPort.DisplayPort is highly extensible and includes the ability to remainbackward compatible. An extensive register set is implemented in thesink (display) device to support both new and old features, and otherregisters indicate device status and allow control by the source. Datapackets in the high-speed video interface include pixel data and othervarious control data. The VESA member companies developing the eDPecosystem have added the special features described in this articleusing these DisplayPort features. This will continue, and there isalready discussion about a future eDP v1.5 that will utilize thefeatures of DisplayPort v1.4, recently published in February 2016.

Key features carried over from DisplayPort v1.4 will include FEC(Forward Error Correction) for the video link, which is important whenemploying video compression using DSC. FEC addresses data errors, whichin an uncompressed image can result in an unnoticeable change of asingle pixel, but with compression can result in a visible change acrossa whole block of pixels from a single error. Another feature broughtover from DisplayPort v1.4 will be the ability to carry High DynamicRange (HDR) metadata, allowing eDP to serve as an embedded interface forHDR-enabled displays. This will include support for the current HDR10standard used in Blu-ray and HDMI 2.0b, and future support for moreadvanced HDR formats that will use extended metadata. However, until thepublication of eDP 1.5, the VESA eDP v1.4b Standard will serve as thegoverning specification for embedded displays within PCs and otherdevices over the next few years.

It’s important to emphasize that successful implementation andadoption of standards like DisplayPort and eDP would not be possiblewithout the cooperative efforts of the more than 230 VESA members acrossthe electronics supply chain. All VESA membershave equal access to all work groups, proposals, and draftspecifications. Typically, the organization holds about 10 differentwork group meetings per week, covering various VESA standards, and hastwo or more PlugTests per year open to all members. By participating inthis manner, member companies – ranging from software, chip and displaymakers to consumer, communication and computing product OEMs – are ableto better understand each other’s concerns and challenges, facilitatingmutually beneficial development efforts.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.