Today’s embedded industries focus more on manufacturing RISC processor-based platforms as they are cost and power effective. On the other side, modern embedded applications are becoming more and more sophisticated and resource demanding. Examples of the concerned applications are numerous such as software defined radio, GPS, mobile applications, etc.
The computation requirements of such systems are very important in order to meet real-time constraints and high quality of services. At the same time, the recent advances in silicon technologies offer a tremendous number of transistors integrated on a single chip.
For this reason, embedded hardware designers are directed more and more towards complex RISC architectures, which may contain several pipeline slots, hierarchical memory system (L1 and L2 cache level), and specific execution units such as NEON architecture for ARM CortexA8 processor as a promising solution to deal with the potential parallelism inherent from modern applications.
Recently, the ITRS and HiPEAC roadmaps promote power defines performance and power is the wall. In fact, power consumption is becoming a critical pre-design metric in complex embed ded systems. An efficient and fast design space exploration (DSE) of such systems needs a set of tools capable of estimating performance and power at higher abstraction level in the design flow.
Today, virtual platform power estimation is considered as an important hypothesis to cope with the critical design constraints. However, the development of virtual platform tools for power estimation and optimization is in the face of extremely challenging requirements such as the seamless power-aware design methodology.
In this paper, we propose an efficient power estimation methodology for complex RISC processor-based plat- forms. In this methodology, the Functional Level Power Analysis (FLPA) is used to set up generic power models for the different parts of the system.
Then, a simulation framework based on virtual platform is developed to evalu- ate accurately the activities used in the related power models. The combination of the two parts above leads to a heterogeneous power estimation that gives a better trade-off be- tween accuracy and speed.
The usefulness and effectiveness of our proposed methodology is validated through ARM9 and ARM CortexA8 processor designed respectively around the OMAP5912 and OMAP3530 boards. This efficiency and the accuracy of our proposed methodology is evaluated by using a variety of basic programs to complete media bench- marks.
Estimated power values are compared to real board measurements for the both ARM940T and ARM CortexA8 architectures. Our obtained power estimation results provide less than 3% of error for ARM940T processor, 3.5% for ARM CortexA8 processor-based system and 1x faster compared to the state-of-the-art power estimation tools.
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