Power management, 2011
From Microchip's eXtreme Low Power to TI's OMAP, new chips contain some interesting and complex power management techniques.
The first decade of this century was surely a story of wireless connectivity. Billions of people now have cellular connections, and many have smart phones that—astonishingly—put the Internet into our pockets. 2010 saw the success of always-connected tablets, such as the iPad, and 2011 promises to see the release of a veritable zoo of similar products.
But the back story is more interesting and nuanced. These portable devices run for hours to weeks off batteries that make the proverbial cigarette pack look monstrous. Yet the CPU runs at hundreds of MHz, with tens of GBs of various forms of semiconductor memory. That half-pound phone has the compute horsepower of the recently-retired desktop rotting in your basement. The secret sauce behind portable electronics is the power management hardware and software, consisting of hundreds of thousands of lines of code and big chunks of silicon.
Most microcontrollers today have at least a few power-saving sleep modes. But you will likely be surprised—shocked even—at the range of low-energy resources provided by the processors behind the portable connectivity revolution.
But first, a little background. Where does the power go?
Most of the energy supplied to a CPU is consumed in three different ways (there are some other current sinks but their importance is small). The first is driving I/O pins. A differential driver can take a fair amount of oomph, but in a typical connected mobile device the processor generally drives high impedance signals, and so these I/O lines represent a small portion of the energy used.
Leakage and dynamic current requirements eat most of the power drawn by a processor. Leakage is just that: electrons that sneak through the silicon from power to ground. The effect is complex but is proportional to the applied voltage and the intrinsic leakage of the material. The latter grows substantially as the transistor sizes shrink; in fact, it grows by about five orders of magnitude as the geometry goes from 250 nm to 65 nm. (A white paper from Altera explains the leakage problem).1
To make matters worse, leakage increases with temperature, to the tune of about an order of magnitude increase per 100°C.2 The effect is an insidious feedback loop: the chip gets hot, so it leaks more, making it even hotter, all the while sucking ever more power. And that's the static dissipation, before the clocks are turned on, before the chip is doing anything useful.
With small geometries typically a third to a half of the power consumed is to leakage.
Dynamic current comes from charging the capacitive loads on the chip, since:
Every bit switch charges a capacitor (for instance, a transistor's gate). Typical advanced processors have hundreds of millions of transistors switching at a furious pace so even tiny amounts of per-transistor current adds up fast. Really fast. For instance, a high-end Pentium may consume 100 amps at times.
The dynamic power consumed by a processor is approximately:
where C is capacitance, f is the clock frequency, v is the applied voltage, and α is the percentage of the circuit that switches with each clock transition.
That formula is a little simplistic as it assumes the CPU is running at a constant speed all of the time. Since even simple microprocessors employ sleep modes it's more useful to think in terms of the amount of power consumed per work-item accomplished. If you have to do one thing and then shut the system down till there's something else needing attention, the energy used per task is:
E = Pt (3)
where t is the time spent accomplishing the task. Substituting:
E = αCfv2t (4)
Given that power is proportional to the voltage squared, it's critical to minimize V. Alas, lowering the voltage limits the maximum frequency attainable, which means the system must be out of a sleep mode longer to get a particular bit of work done.
To paraphrase that last sentence: ft is a constant for a given task. However, if the processor must be awake for more than doing one particular activity, cutting the clock frequency may be a better way to save power.
Most of us have programmed various sleep modes in our microcontrollers, and generally this is a pretty simple process. Texas Instruments' MSP430 is touted as an "ultra-low power" controller, and indeed contains about 25 registers associated with setting and monitoring voltage levels.3 It provides about a half-dozen low power modes.
Microchip's eXtreme Low Power controllers such as the PIC16F1827 are also typical.4 The '1827 has a single very-low-power sleep mode controlled by a dozen registers, and its onboard peripherals may or may not be active during sleep.
Then there are the connected mobile device parts, which come with vastly more sophisticated power-management features.