Will Moore's Law doom multicore?

March 11, 2013

Jack Ganssle-March 11, 2013

Moore's Law means more transistors per chip, but will those power-sucking semiconductors doom multicore?

In 1974 Robert Dennard came up with a scaling theory that drew on Moore's Law to promise ever-faster microprocessors. If from one generation to the next the transistor length shrinks by a factor of about 0.7, the transistor budget doubles, speed goes up by 40%, total chip power remains the same, and a legion of other good things continues to be bestowed on the semiconductor industry.

Unfortunately Dennard scaling petered out at 90 nm. Clock rates stagnated and power budgets have grown at each process node. Many traditional tricks just don't work any more. For instance, shrinking transistors meant thinner gate oxide thicknesses, but once those hit 1.2 nm (about the size of five adjacent silicon atoms), tunneling created unacceptable levels of leakage. Semiconductor engineers replaced the silicon-dioxide insulator (with a dielectric constant of 3.9) with other materials like hafnium dioxide (dielectric constant = 25), to allow for somewhat thicker insulation. Voltages had to go down, but are limited by subthreshold leakages as the transistors' threshold voltage must inevitably decline. More leakage means greater power dissipation. A lot of innovative work is being done, like the use of 3D finFETs, but the Moore's manna of yore has, to a large extent, dried up.

Like the cavalry in a bad western, multicore came riding to the rescue, and it's hard to go a day without seeing some new many-core CPU introduction. Most sport symmetric multiprocessing architectures, where two or more cores share some cache plus the main memory. Some problems can really profit from SMP, but many can't. Amdahl's Law tells us that even with an infinite number of cores, an application that is 50% parallelizable will get only a 2x speedup over a single-core design. But that law is optimistic, and doesn't account for the inevitable bus conflicts that will occur when sharing L2 and main memory. Interprocessor communication, locks, and the like make things even worse.

Data from Sandia National Labs shows that even for some very parallel problems multicore just doesn't scale after a small number of processors are involved.

In Power Challenges May End the Multicore Era (Communications of the ACM, February 2013, subscription required), the authors develop rather complex models that show multicore may (and the operative word is "may") bang into a dead-end due to power constraints. Soon.

The key takeaways are that by the 8-nm node (expected around 2018) more than 50% of the transistors on a microprocessor die will have to be dark, or turned off, at any one time just to keep the parts from self-destructing from overheating. The most optimistic scenarios show only a 7.9x speedup between the 45-nm and 8-nm nodes; a more conservative estimate pegs that at 3.7x. The latter is some 28 times less than one would expect from the gains Moore's Law has led us to expect.

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