Relearning pc-board design in the era of sub-20 nm ICs
One of the more visited design articles on the Embedded.com site recently has been three-part series by Walt Kester about the problems facing embedded systems hardware developers in designing and building printed circuit boards. Complementing this series are a number of other articles, white papers and webinars on this topic. Some of my Editor’s Top Picks on this topic include::
guide to better EMC for pc-board design
Ensuring the thermal integrity of your PC-board design
Correct-by-construction pc-board techniques and tools
Write your own PCB design rule checker
Addressing EMI test challenges in nextgen PCB designs
Capturing and sharing Intellectual Property in PCB design
Designing high speed PCBs with a parallel design methodology
Using constrain management to ease board design
Not only are Intel and Micron building 25 nm NAND devices, but Samsung is seriously considering a move to sub-20 nm geometries. Complicating the issue is that in order to increase the functional density of the ICs, so-called 3-D chip packaging is being considered, in which chips are stacked vertically and connected one to the other by means of through-silicon vias.
Such chip level advances will only make the problems PCB hardware designers face even tougher – thermal profiles, crosstalk, electrostatic discharge, electromagnetic interference, and routing issues, to name a few. That makes their role in the embedded systems design process even more important and deserving of even more intensive coverage.
So I would like to hear from you about your ideas for design articles: what you would like to read and write about, the problems you face and the tools and techniques you are using to deal with them. (Embedded.com Editor Bernard Cole, firstname.lastname@example.org, 928-525-9087.