Is low power driving move to integrated HW/SW codesign?

July 06, 2011

Bernard Cole-July 06, 2011

Many pressures are driving embedded systems developers to higher level tools to integrate hardware/software design, debug and verification: larger code sizes; more complex processors or SoC architectures; and the need for more reliability and security. But perhaps the most potent driver of all is the compelling need for lower power and more energy-efficient operation without sacrificing performance.

Solving this demanding and difficult equation often forces designers to search outside their particular areas of expertise for answers: software developers are learning much more about the processor architectures and the underlying chip-level logic design; semiconductor process engineers are becoming more aware of what the software/hardware application environment demands; and SoC processor architecture designers are dealing with both.

In their quest for solutions, embedded developers are also moving to high level tool environments that allow teams of engineers to move back and forth between several levels of the design. For example, in “Using SystemC to build a system-on-chip platform,” TI’s OMAP team describes the wide array of hardware and software tools they used to build, simulate, and test hardware and software that achieve high performance at low power.

In “Reduce SoC device/package leakage/power with improved power management protocols,” Freescale process engineers describe how an understanding of the packaging and pinout requirements of their SoC design allowed them to develop a chip-level protocol that significantly reduces power. In “Managing power in embedded applications using dual operating systems,” Loc Truong details how appropriate use of RTOS features such as interprocess communication and state machines can further reduce power demands beyond what developers have been able to achieve in hardware alone.

Re-enforcing my suspicion that it is the need for lower power designs that do not sacrifice performance which is driving this shift were the many articles I found and included in a recent Tech Focus newsletter on this topic. Out of all of them, the ones that best described this delicate balancing act are:

Using drowsy cores to lower power in multicore SoCs
Choosing the right low power processor for your design
The why, where and what of low-power SoC design
What is power aware debugging?

What tools and techniques are you and your teammates using to coordinate this delicate dance between hardware and software design? Between high performance and low power? Which ones work and which do not? What tools do you need to satisfy these conflicting requirements? What has been your experience and what do you think other developers need to keep in mind?

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