The MCU guy's introduction to FPGAs: The Hardware

April 24, 2015

Max The Magnificent-April 24, 2015

A lot of my friends are highly experienced embedded design engineers, but they come from a microcontroller (MCU) background, so they often have only a vague idea as to what an FPGA is and what it does. When pressed, they might say something like "You can configure an FPGA to do different things," but they really have no clue as to what's inside an FPGA or how one might be used in a design.

The thing is that MCUs are great for some tasks, but not so good at others. When it comes to performing lots of computations in parallel, for example, FPGAs will blow your socks off (so make sure you're wearing elasticated socks before you start playing with these devices). In this column we'll consider the hardware aspects of the FPGA universe; we then take a look at the FPGA equivalent to MCU software in The MCU guy's introduction to FPGAs: The Software.

Simple FPGA fabric
In the context of an integrated circuit, it's common to hear the term fabric, which is used to refer to the underlying structure of the device. (As a point of interest, the word "fabric" comes from the Middle English fabryke, meaning "something constructed.") Let's start with the core programmable fabric inside an FPGA...

If we were to peer inside the FPGA's package, we would see its silicon chip (the technical term is the die). The programmable fabric is presented in the form of an array of programmable logic blocks as shown in the image below. If we "zoom in" with a metaphorical magnifying glass, we see that this fabric comprises "islands" of logic (the programmable logic blocks) basking in a "sea" of programmable interconnect.

A generic representation of fundamental FPGA programmable fabric.

Why yes, I did create this image with my own fair hand, and I am indeed rather proud of it. Thank you so much for noticing (grin). If we zoom in further, we see that each of the programmable blocks contains a number of digital functions. In this example, we see a 3-input lookup table (LUT), a multiplexer, and a flip-flop, but it's important to realize that the number and types and sizes of these functions varies from family to family.

The flip-flop can be configured (programmed) to act as a register or a latch; the multiplexer can be configured to select an input to the block or the output from the LUT; and the LUT can be configured to represent whatever logical function is required.

A closer look at LUTs
Our simple example shown above featured a 3-input lookup table (LUT). In the real world, even the simplest FPGAs use 4-input LUTs, while larger, more sophisticated devices may boast 6-, 7-, or 8-input LUTs, but we'll stick with a 3-input version for the sake of simplicity.

We will be discussing the various types of FPGA implementation technologies in a future column. For the moment, we need only note that the programmable elements inside the FPGA may be implemented using antifuses, Flash memory cells, or SRAM memory cells. Let's first consider an FPGA created using an antifuse technology. This is a one-time programmable (OTP) technology, which means that once you’ve programmed the FPGA it stays that way forever.

The easiest way to visualize this is as a cascade of 2:1 multiplexers (MUXs) as shown below. In the case of our antifuse-based FPGA, programming the device would essentially "hardwire" the inputs to the first wave of MUXs to the appropriate 0 and 1 values required to realize the desired logical function. The values shown in the illustration below reflect the fact that we are using this LUT to implement the equation y = (a & b) | c from the previous image. In reality, the MUXs would be implemented using a branching “tree” of FETs, but we really don’t need to worry about the lowest-level implementation details here.

An antifuse-based LUT in which the input values are "hardwired" (left) and an
SRAM-based LUT in which the inputs are fed from SRAM cells (right).

Another very common type of FPGA implementation technology is based on the use of SRAM configuration cells. Once again, we will consider this in more detail in a future column. All we need to note here is that when the board is first powered-up, the SRAM-based FPGA is loaded with its configuration (we can think of this as programming the device). As part of this configuration, the SRAM cells acting as inputs to the LUT’s multiplexers are loaded with the desired 0 and 1 values as illustrated above.

I’ve not shown the mechanism by which the 0s and 1s are loaded into the SRAM cells because I don’t want to confuse the issue. For the purposes of these discussions, we really don’t need to worry about how this “magic” takes place. The only thing I will mention here (to give you something to ponder) is that -- using a technique called partial reconfiguration -- it is possible for one part of the FPGA to instigate the reconfiguration of another part of the FPGA (and vice versa, of course). For those readers coming from a microcontroller and/or software background, we might think of this as being the hardware equivalent of self-modifying code. This means that this technique is very, very powerful, but it comes with the capability to introduce problems that are horrendously difficult to isolate and debug.

General-purpose inputs and outputs
The device will also include general-purpose input/output (GPIO) pins and pads (not shown in the above illustration). By means of its configuration cells, the interconnect inside the device can be programmed such that the primary inputs to the device are connected to the inputs to one or more programmable logic blocks. Also, the outputs from any logic block can be used to drive the inputs to any other logic block and/or the primary outputs from the device. Furthermore, the GPIO pins can be configured to support a wide variety of I/O standards, including voltages, termination impedences, slew rates, and so forth

The very first FPGA was similar to the architecture discussed in this column. Introduced by Xilinx in 1985, the XC2064 (which was created at the 2um technology node) contained an 8 x 8 = 64 array of logic blocks, each containing a 4-input LUT along with some other simple functions. Since that time, FPGAs have evolved dramatically, as we shall see...


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