SYZYGY: The Goldilocks connection standard for FPGA-based systems
We all know the story of the little girl named Goldilocks -- an unruly miscreant who breaks into an unsuspecting family's home and wantonly taste-tests the three bowls of porridge she finds there. Being somewhat finicky, she decides that the first one she spoons into her mouth is too hot; and the next is too cold; but the third bowl is just right so she gobbles it all up.
Well, until now, the FPGA landscape has enjoyed only the extreme cold and hot bowl options with regards to connecting peripherals into FPGA systems. At one end of the scale we have Digilent's Pmod standard, which is ideal for low-speed peripherals in the 1 to 50 MHz range. The 6-and 12-pin connectors are inexpensive to implement, and the cost of the peripherals -- of which there are many off-the-shelf offerings -- is around $8 to $50.
(Source: Opal Kelly)
At the other end of the spectrum we find the ANSI/VITA standard known as FMC (FPGA Mezzanine Card), which is more suited to high-performance peripherals with data rates up to 10 Gbps. In this case, the 72-pin and 200-pin connectors are much more expensive, and the peripherals themselves can cost anywhere from a couple of hundred dollars to thousands of dollars.
(Source: Opal Kelly)
So, what are you going to do if you have a brilliant idea for a peripheral board whose pin and performance requirements fall somewhere between the capabilities offered by Pmod and FMC? Of course, a mind-boggling variety of connection solutions are available, but there's a world of difference between selecting a connector at random versus using a standard solution that works with a wide range of systems from other vendors.
All of which brings us to the folks at Opal Kelly, who are well known for providing a range of powerful USB and PCI Express FPGA-based Integration Modules that connect a user's hardware design implemented in an FPGA to the user's software implemented on a PC. In the case of USB, for example, Opal Kelly handles all of those pesky little details, such as the enumeration process, low-level drivers, and bus timeouts (you can get a really good idea about how this all comes together by reading this column that I penned some time ago).
For some time now, Opal Kelly's customers have been bemoaning the fact that there was no good standard connectivity solution falling between the Pmod and FMC domains. In order to address this "hole," the guys and gals at Opal Kelly have just announced the release of SYZYGY, a new open standard for connecting high-performance peripherals to FPGA hardware.
As an aside, "syzygy" is a real word -- it's an astronomical term that refers to three celestial bodies being in alignment, such as the sun, moon, and earth during a solar or lunar eclipse (see My First Total Solar Eclipse Was Awesome!)
SYZYGY is intended to fill the need for a compact, low cost, low pin-count, high-performance connectivity solution between FPGAs and single-purpose hardware peripherals. Devices for high-speed data acquisition, digital image capture, software-defined radio, and digital communication were the primary inspiration for the development of SYZYGY.
The SYZYGY specification defines two connector types: Standard and Transceiver. The Standard SYZYGY connector offers up to 28 single-ended, impedance-controlled signals, 16 of which may be defined as differential pairs for interface standards such as LVDS. The Transceiver SYZYGY connector boasts four lanes of Gigabit-class transceiver connections and also offers up to 18 single-ended signals. The Transceiver connector is intended for use with JESD204B data acquisition, SFP+ transceivers, and other devices requiring high-speed SERDES. Both Standard and Transceiver connectors have optional low-cost, high-performance coaxial or twinaxial cable assemblies.
GPIO (blue) and Transceiver (orange) solutions (Source: Opal Kelly)
As we see, SYZYGY's "sweet spot" falls between Pmod and FMC. SYZYGY is in no way intended to replace or supplant Pmod or FMC; for low pin-count, low-speed, inexpensive peripherals, Pmod is still the way to go; for high pin-count, extreme-performance, high-cost peripherals, FMC may well be the best choice; but if you need moderate pin-counts coupled with high-performance and low solution costs, then SYZYGY is going to bring a smile to your face.
Designed to accommodate the wide range of I/O voltages common with FPGA systems, SYZYGY defines SYZYGY DNA and SmartVIO. SYZYGY DNA is a simple way for peripherals to communicate personality data to the carrier, such as manufacturer name, product name, and serial number. SmartVIO is included in the DNA payload and defines the range of I/O voltages accept¬able to the peripheral so that carriers can set I/O voltages accordingly.
In order to allows users to evaluate this new standard, Opal Kelly offers an open-source FPGA-based SYZYGY-compatible carrier called the SYZYGY Hub.
SYZYGY Hub (Source: Opal Kelly)
The SYZYGY Hub offers three standard SYZYGY ports, one transceiver SYZYGY port, SmartVIO power delivery, a Xilinx Zynq SoC FPGA with Linux OS, 1 Gb Ethernet, 1 GiB DDR3-800, USB Type-C (host and device modes), USB Serial UART (console access), and 5V to 18V power input.
Opal Kelly has offered SYZYGY as an open standard and free to license by carrier and peripheral manufacturers. This licensing approach is intended to encourage consistency, proliferation, and a healthy ecosystem where carrier and peripheral manufacturers, semi-conductor device manufacturers, educational institutions, and research organizations are invited to develop their own additions.
For more information, or to download the SYZYGY Standard, please visit SYZYGYfpga.io