AI IC research explores alternative architectures
ANTWERP, Belgium — Imec said at its annual event here that it is prototyping a deep-learning inference chip using single-bit precision. The research institute hopes to gather data over the next year on the effectiveness for client devices of the novel data type and architecture--either a processor-in-memory (PIM) or an analog memory fabric.
The PIM architecture, explored by academics for decades, is gaining popularity for data-intensive machine-learning algorithms. Startup Mythic and IBM Research are designing two of the most prominent efforts in the field.
Many academics are experimenting with 1- to 4-bit data types to trim the heavy memory requirements for deep learning. So far, commercial designs for AI accelerators from Arm and others are focusing on 8-bit and larger data types, in part because programming tools such as Google’s TensorFlow lack support for the smaller data types.
Imec had the logic portion of a 40-nm accelerator built in a foundry and is now adding an MRAM layer in its own fab. It simulated the performance of the design using SRAM and estimated design rules for a 5-nm node.
The effort is part of an Imec research program still in development with at least two unnamed integrated device manufacturers as partners. The program got its start nearly two years ago and quickly prototyped a PIM design at 65 nm using a form of resistive RAM.
The 65-nm chip was not focused on deep-learning algorithms, although it powered a fascinating demo of a computer composing music. It learned patterns using a time-series analysis based on data in the form of music streamed from sensors.
The 40-nm Low-Energy Neural Network Accelerator (LENNA) will tackle deep learning head-on, computing and storing binary weights in relatively compact MRAM cells. It will act as a test chip, providing results on the pros and cons of the effectiveness of the architecture, different memories, and binary data types.
“Our mission is to define what semiconductor technologies we should develop for machine learning using emerging memories — we may need process tweaks” to get optimal results, said Diederik Verkest, a distinguished member of technical staff in an interview.
“AI will be a driver for how process technology roadmaps evolve, so Imec will put a lot of effort on AI and [PIM architectures] — how this plays out will be a big deal,” said An Steegen, executive vice president for semiconductor technology and systems at Imec.
Indeed, AI marks “a fundamental shift in computing,” said Nigel Toon, chief executive of startup Graphcore, which is rolling out its first chips later this year.
“Today’s hardware holds us back; we need something more flexible … we want to see [neural-network] models be able to adapt based on experience,” said Toon in a plenary talk at the Imec Tech Forum here.
As an example, Toon said that two years ago, Google interns spent $250,000 just on electricity trying to optimize a neural-network model on the search giant’s data centers that use traditional x86 CPUs and Nvidia GPUs.
>> Continue to page 2 on our sister site, EE Times: "AI chip tests binary approach."