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NAND roadmaps highlight power, performance

August 09, 2018

rick.merritt-August 09, 2018

SAN JOSE, Calif. — Four established 3D NAND flash makers showed at least small pieces of their roadmaps in keynotes at the Flash Memory Summit here. Their latest rival, Yangtze Memory Technology Corp. (YMTC), gave a deeper dive into its technology and business outlook in a meeting with press.

SK Hynix was the most forthcoming of the established players, providing details of its 96-layer devices. Toshiba announced a low-latency chip geared to compete with Samsung’s Z-NAND and Intel’s Optane. Micron only gave a brief glimpse of its next-generation plans, and Western Digital rolled out new software as part of a data center strategy.

The news comes at a time when hard disk drives still dominate computer storage. However, NAND flash is on a tear, expected to make up as much as half the market by 2025, according to some market projections.

SK Hynix announced that it will sample before the end of the year a 512-Gbit version of its 96-layer chips in an 11.3 x 13-mm2 package for mobile systems. Before June, it will sample a Tbit version of its so-called V5 family in a 16 x 20-mm2 package. Both chips use a charge-trap architecture and support data rates up to 1.2 Gbits/s/pin.

The V5 parts are 30% smaller than its current 72-layer NAND chips. They provide a 25% boost in read and 30% boost in write performance. Overall power efficiency is up 150% compared to its current products.

SK Hynix is already working on a next generation with 128 layers. It expects to eventually deliver chips with more than 500 layers that pack 8 Tbits into a single package, said Hyun Ahn, a senior vice president of NAND development and business strategy for the company.

For its part, the newly reformed Toshiba Memory Corp. said that it will start production early next year on a 1.33-Tbit chip. It will be a Gen 4 version of its BiCS architecture using 96 layers and 4 bits/cell.

Separately, Toshiba announced XL-Flash, a chip sporting one-tenth of the random-read latency of its current 3-bits/cell parts. The component uses shorter word lines and more planes but otherwise leverages the existing BiCS process and interfaces.

The company, which claims leading market share for SATA drives, said that the interface will die off in about two years, replaced by SAS and NVMe drives. The event was a showcase for several NVMe drives using PCI Express Gen 4.

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The XL-Flash will compete wth Samsung’s Z-NAND and Intel’s Optane. Click to enlarge. (Image: Toshiba)
 
>> Continue reading page two of this article on our sister site, EE Times: "NAND makers up flash ante."

 

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