Advertisement

RISC-V ISA IP proliferates

December 04, 2018

rick.merritt-December 04, 2018

SAN JOSE, Calif. — RISC-V is open for business, proponents will claim at the first annual summit for the open-source instruction set architecture today. The Silicon Valley event comes at a time when backers say that China is rallying around the architecture with perhaps hundreds of RISC-V SoCs and dozens of cores in the works.

At the event, Western Digital will detail a 32-bit embedded core that it will use in a controller for a consumer solid-state drive set to ship in 2020. It is releasing as open-source both the core and a protocol for a cache-coherent interconnect for RISC-V processors — and it has started work on a 64-bit core.

The Microsemi division of Microchip will describe a five-core complex that it will embed in its PolarFire FPGAs by early 2020. The chip marks its first step in a plan to standardize on use of RISC-V.

In the hot field of machine learning, startup SiFive will describe two RISC-V chips — an embedded inference device based on Nvidia’s Deep Learning Accelerator and a training chip using newly mined RISC-V vector extensions along with HBM2 memory and 56-Gbit/s SerDes.

Separately, Google, an early member of the RISC-V Foundation, will show its TensorFlow Lite software geared for embedded systems running on the Zephyr operating system on a RISC-V chip. For its part, Bitmain, a leader in bitcoin-mining silicon, will reveal that its Sophon Edge AI chip announced last year uses a RISC-V core as its sensor hub.

Korean startup Fadu will describe an SSD controller made in a 7-nm process and based on a 64-bit RISC-V core. Startup Esperanto, which debuted at a RISC-V workshop last year , will describe its ET-Maxion, a high-frequency, out-of-order RISC-V core being designed for TSMC’s 7-nm process.

The event will also host keynotes from NXP, Qualcomm, and Facebook’s AR/VR chip-design group. It will include multiple sessions on RISC-V’s security architecture as well as news from tool vendors.

Western Digital will release open-source code for its 32-bit Swerv core by April. (Image: WD)

“We are really happy with the progress that the ecosystem has made in the past year,” said Martin Fink, chief technology officer of WD, noting that big names such as Tesla and several tool vendors joined the foundation last year. “Next, we’d like to see full endorsements from foundries such as TSMC and GlobalFoundries.”

“I think the ecosystem is about ready to pop … this is the first commercial RISC-V summit, and it’s a seminal event,” said Tim Morin, director of product marketing for Microchip’s FPGA business.

RISC-V has a negligible slice of the processor IP market that Arm dominates today, with 21.3 billion units shipped in 2017. However, it is gaining steam and is well-suited to embedded, automotive, and IoT apps that are tolerant of its lack of broad support from third-party software, said analyst Linley Gwennap at an event earlier this month hosted by core provider Andes .

The architecture would benefit greatly if Google ported Android to it and it got more attention from RTOS vendors, he added.

To date, SiFive has delivered as many as 400 RISC-V systems running Linux. Another batch may be on the way soon to help seed a budding community of software developers.

>> Continue reading page two of this article on our sister site, EE Times: "RISC-V Takes a Leap Forward."

 

 

Loading comments...

Most Commented