Atmel aims metal programmable ARM MCUs at FPGAs, ASICs and ASSPs
San Jose, Ca. - Atmel Corp.
this week said it is going into volume production on a
new category of customizable metal programmable 32-bit ARM-based
microcontrollers it calls Customizable Atmel Processors (CAP).
Not quite standard products, not quite an FPGAs, nor a gate array/standard cell ASICs, the company claims the new ARM7 and ARM9-based CAP devices have features and capabilities of all of these alternatives, but fit into a price and performance niche that none of these can adapt to quite as easily, if at all.
As if that were not enough, unlike FPGA and ASIC vendors who require that customers make their own arrangements with ARM Ltd., there are no license fees or royalties charged for the ARM cores implemented by the user in the CAP devices, with the cost absorbed by Atmel.
According to Jay Johnson, director of ASIC marketing at Atmel, the new AT91CAP Customizable Atmel Processor (CAP) devices deliver as much as 8X the performance for DSP algorithms that are frequently implemented in FPGAs, with substantially reduced power consumption and unit IC costs that are 30% to 50% lower. The new CAP devices will be extensions of Atmel's existing 32-bit ARM7-, ARM9-, ARM11-based AVR32UC3, and AVR32 AP7 microcontroller families."The number of designs with signal processing is exploding," he said. " So far, designers have been limited to three options for algorithmically complex designs: a DSP processor, an FPGA or a custom ASIC. "FPGAs have made significant inroads into this market because they implement DSP functions faster than DSP processors and do not require the huge volumes and NREs associated with ASICs.
However, FPGAs have notoriously high power consumption and their performance is a fraction of that of custom ICs. <>Like all Atmel's 32-bit microcontrollers, AT91CAP MCUs include an Atmel processor core, a variety of peripherals (each with its own DMA), and multiple high-speed busses.
Metal Programmable Cell Fabric at the core
But what makes the new customizable processors unique is a metal programmable block (MP block) with up to two-million FPGA-equivalent gates that can be used to implement any of the following: 1) DSP algorithms or other IP commonly implemented in FPGAs, 2) one or more additional processor cores or 3) additional peripherals not currently available on Atmel's standard product ARM7- and ARM9-based MCU families.
The result of a two- to three-year- development effort, the metal programmable logic block is an outgrowth of a technique originally developed by Atmel's standard cell design group to allow company designers to quickly develop standard products for fast growing and developing market segments.
"What we saw as we proceeded was that there was an even greater opportunity if we could develop a methodology that would allow developers to quickly generate variations of standard products optimized for their particular needs," said Johnson, "without the cost, die size or performance burden that FPGAs imposed."
Where the original standard cell process used a two layer metallization, the Metal Programmable Cell Fabric (MPCF)-based logic block has six layers which are customizable at metallization and therefore has much more efficient routing and requires fewer transistors to implement the same logic as an SRAM-based reprogrammable FPGA. The smaller number of transistors reduces both silicon area and power consumption, while also minimizing logic delays.
Incorporating a compact 8-transistor core cell that can be configured into more than 400 different functional elements using a custom-developed library, Johnson said the MPCF's efficient cell routing and additional metal layers provide much higher transistor and placement utilization than alternative technologies.
"With routed gate densities nearly identical to those of standard cells ASICS, in the same process technology, MPCF technology makes CAP MCUs 30% to 50% less expensive than the comparable MCU-PLUS-FPGA solution are even cost-competitive with standard cell ASICs," he said.
By integrating a system's unique IP and glue logic on-chip with the MCU, said Johnson, the on- and off-chip delays associated with comparable FPGA implementations is eliminated with the logic capable of being run at full bus speed with zero wait states. "The MP block is capable of clock rates of 400 MHz or more, potentially increasing performance of FPGA logic implemented in the MP block by 8 times," he said.
To allow developers the maximum of flexibility in their use of the metal programmable logic block, the AT91CAP-enabled MCUs have a multilayer bus matrix with multiple bus masters dedicated to the MP block that eliminate bus contention and maximize on-chip bandwidth.
For example, one of the new devices in the family, the ARM7-based AT91CAP7, has a six-layer bus with four bus masters dedicated to the MP block for maximum on-chip bandwidth of 19.2 Gbps. The other device, the ARM9-based AT91CAP9, has an 12 layer bus with three bus masters dedicated to the MP block for a 38.4 Gbps maximum on-chip bandwidth.
MPCF-based CAPs are multicore-able
The metal programmable approach is also very multi-core friendly, especially if the developer has a design that involves both a standard ARM configuration with some customized core variation. The MP block on the CAP9 devices, said Johnson, was designed to enable the implementation of a second ARM926EJ-S core with caches.
"Alternatively, it can also implement an AVR32 core or multiple 8-bit cores, allowing designs with multiple MCUs to be completely integrated on a single system-on-chip (SoC)," he said. "For example, sensor-rich industrial control systems frequently require 8-bit MCUs for each sensor in the system.
"Multiple 8-bit MCUs can be integrated on a CAP-enabled device, reducing cost, power consumption and system complexity. Bus master controls and DMA access can be provided between the MP block and the system bus to provide maximum connectivity for the additional processors."
Based on the ARM7TDMI processor core, the AT91CAP7S MCUs come with customizable logic equivalent to approximately 28K or 50K FPGA LUTs or 250K or 450K routable ASIC gates. The ARM9-based AT91CAP9S integrates a 200 MHz ARM926EJ-S core with 16 KBytes each of program and data cache, and customizable logic equivalent to approximately 28K or 56K FPGA LUT's (250K or 500K routable ASIC gates).
Any existing ARM7/9 -plus-FPGA design can be migrated to a AT91CAP
device, said Johnson. "Even with the high degree of customization
in a AT91CAP device, the NRE is only $150,000 including mask,
engineering charges, and prototypes," he said.