FPGA tool upgrade slashes runtime
Microsemi’s Libero SoC design suite V12.0 reduces design flow runtimes, while providing a unified platform for multiple FPGA families, including the latest PolarFire production releases. Improving designers’ productivity, Version 12.0 software achieves a runtime reduction of 60% for timing, 25% for place and route, and 18% for power results.
The suite integrates Synopsys Synplify Pro synthesis and Mentor Graphics ModelSim simulation with constraints management, programming and debug tools, and secure production programming support. In addition to the improvements mentioned above, Libero V12.0 increases quality of results by 4% for larger designs and 10% for the PolarFire MPF300-TS-1 device. It also supports the radiation-tolerant RT4G150L FPGA, which offers a 25% savings for the standard speed grade.
This unified design suite for PolarFire, IGLOO2, SmartFusion2 and RTG4 FPGAs eliminates the need for designers to qualify multiple pieces of software when working across product families. Libero SoC V12.0 now supports FPGA hardware breakpoint for RTG4 and PolarFire devices, PCIe debug support for PolarFire, and continuous transceiver eye monitoring using SmartDebug. Improvements in DDR memory performance is an average of 29% in high-effort mode and 39% in regular-effort mode.
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