Eliminate design complexity using Aldec's HES Accelerator - Embedded.com

Eliminate design complexity using Aldec’s HES Accelerator

This “Product How-To” article focuses how to use a certain product in an embedded system and is written by a company representative.

During IC design and development, hardware acceleration simulation isgenerally performed at the system integration and test stage, prior tochip burning (for FPGAs) or tape-out (for ASICs). Hardware accelerationsimulation is done to eliminate the performance bottleneck commonlyobserved in software simulators and to increase the speed of systemsimulation by a thousand times.

Hardware acceleration simulation provides the high-speed featuresnot available in software simulation, as the simulation speed borderson the real speed of the final product when the object is verifiedusing hardware.

However, this high-speed feature is compromised with the reductionof the method's debugging capabilities. And one issue confrontinghardware acceleration simulation is how to provide the debuggingcapabilities needed in high-speed simulation.

More challenges surface when one performs hardware accelerationsimulation in SoC and ASIC design. The NRE expense for ASICs and SoCsis rapidly increasing. Thus, when a chip fails to roll on time, theproduct's time-to-market and development cost increase accordingly.

Figure1. HES performs HW acceleration simulation, SoC HW/SW accelerationco-verification, and HW prototype verification.

Hardware simulation
About 60-90 percent of IC design and development time is dedicated todebugging, simulation verification, prototype verification and hardwaretest. Improving veri- fication efficiency is key to fastertime-to-market and the fulfilment of increasingly complex designverification requirements.

Aldec's Hardware Embedded Simulation accelerator (HES) addresses theissues of increasing design complexity and product development time.HES uses incremental prototypes, transplanting modules in users'designs into hardware at different verification stages. Simulationspeed gradually increases with the use of hardware transplants.

Verification takes days in traditional HDL software, while HES takesseveral minutes to implement. HES targets embedded systems such as ARMand MIPS as well as storage devices, increasing simulation verificationspeed and HW/SW co-verification flexibility.

HES communicates with the master computer via the PCI bus interface.The hardware acceleration board in HES uses a 32bit or 64bit PCI bus toconnect the software and hardware, and consistent simulation speeds forhardware and software components. HES connects the hardware model withthe software simulator through the Design Verification Manager (DVM)tool.

The DVM combines with any software simulator to provide reliable ICverification. HES implements concatenation through the daughter-boardinterface to meet verification requirements of large systems. It alsosupports networked team design.

The board has different models and supports multiple FPGAcomponents. Designers can select the board according to the scale ofthe design. One HES board supports designs of up to 1,200 lines, andmultiple concatenated boards can verify design of up to 4,800 lines.

HES also provides solutions for designs with many storagecomponents. An ordinary HES board has 128Mbit storage, including DDR,SDRAM, SSRAM and DPRAM. It is only necessary to set up external storagevia the DVM (except for FPGA chips).

For high-capacity storage designs (above 128Mbit), an HES board withhigh-capacity storage is recommended. The user can concatenate multipleHES boards to increase the acceleration simulation capability fordesign and storage.

The user can also ensure high-capacity storage by inserting daughterboards. The figure shows how quickly the HES system implements hardwareacceleration simulation, including system HW/SW accelerationco-verification on the SoC.

Intelligent simulation
HES can quickly do hardware-acceleration simulation for systemintegration test. Using an open API solution, engineers can developuser-defined test applications such as interactive control softwarewith GUI.

The DVM tool distributes design codes to multiple FPGA chipsautomatically, and converts ASIC codes to FPGA codes, includingconversion from access control clock logic to clock enable logic, aswell as automatic conversion of storage IP. HES also provides aninternal debugging capability. In the DVM, the user can specify theRTL-level or netlist-level internal signals to be traced and let theDVM perform operations such as code modification automatically.

Use an API to develop the C/C++ test excitation program without HDLsimulator. The DVM tool provides the C/C++ API for this. Through theAPI, the user can directly access and control hardware- accelerationboards (e.g. develop C-based test excitation and interactive controlsoftware with GUI).

Generally, the HDL software simulator limits the performance of thehardware-acceleration simulation system. By writing the C/C++ testexcitation program independently of the simulator, this performancebottleneck caused by the simulator is eased.

Figure2. The Aldec HES board has 128Mbit storage, including DDR, SDRAM, SSRAMand DPRAM.

Apart from developing the C/ C++ test excitation program, the usercan also implement more advanced applications such as those with GUI inthe Visual C++ environment. The DVM can generate basic C-Testbenchcodes automatically, in which basic API function invocation isincluded, such as the initialization function of thehardware-acceleration board. Using this method, engineers can developuser-defined C codes quickly.

High-speed hardware-acceleration simulation is performed at the riskof decreasing the method's debugging capability. In addition tohigh-speed simulation, the HES system enables debugging of internalsignals.

With the DVM tool, engineers can specify the internal signals to betraced at the RTL level or EDIF netlist level, and the DVM willautomatically do code modification. In the subsequent simulationprocess, engineers can perform operations, including waveformobservation, endpoint setting and signal data flow tracking on internalsignals.

The DVM will automatically implement the PCI interface drivercontrol and programming of PLI, VHPI and FLI language interface.Engineers only need to specify to the DVM which internal signalsrequire simulation debugging.

Automatic distribution
For large designs that cannot be accommodated by a single FPGA chip ora single HES board, multiple HES hardware acceleration boards can beused. Insert the HES boards into the computer mainboards to providehardware resources such as higher-capacity FPGAs. A combination of HESboards can accommodate large designs of up to 100 million lines.

Moreover, the DVM tool can distribute design automatically.Engineers only need to specify the HES board on which the specific codemodules are implemented, and then the DVM distributes and combines thedesign automatically, and implements the final layout and wiring.Engineers may even dispense with specifying the distribution mode, asthe DVM automatically selects the HES board on which the specific codemodules are implemented.

HW/SW co-verification in SoC design has always been a concern ofengineers. In traditional SoC development, the software developmentengineer does not interact with the hardware design engineer until thecompletion of the prototype circuit. Software engineers perform codedesigning and debugging in the software IDE. After code debugging, theyhave to wait for the prototype design.
The software code can only be integrated into the hardware platform forHW/ SW integration test verification after the prototype circuit boardis completed. This explains why many bugs in the HW/SW design are notdetected until the software codes are integrated into the prototypecircuit board. And since bugs are detected later in the design process,development time increases while product design quality decreases.

HW/SW co-verification encourages software and hardware engineers tocollaborate as early as possible. Through HW/SW interaction debugging,most bugs in the design, especially the HW/SW interface bugs, areeliminated early in the development process, thus ensuringbetter-quality designs and faster time-to-market.

The HES system provides SoCs with HW/SW co-verificationcapabilities. By placing the hardware model on the HES hardwareacceleration board and the FPGA chip, HW/SW co-verification speed ismaximized. The HES method can also designate the instruction storage ofthe ARM or MIPS processor kernel to different locations to providedifferent fetching simulation speeds and debugging requirements.

For example, users can place instruction storage into the ARMdaughter boards to obtain the highest fetching speed, or designate theinstruction storage into the HES hardware acceleration board to achievea certain debugging capability at a high fetching speed. Engineers canalso use the instruction storage feature as a hardware model and put itinto the testbench of the HDL simulator to attain the highestinstruction storage action debugging capability.

Implement the prototype verification platform for various IC designsquickly. Long-term real-time test and verification are generallyrequired, particularly at the last stage of the design cycle.Meanwhile, the whole design must be converted into physical circuits.Through real physical excitation signals, the developer conducts teststo verify if the design can work normally in the physical environment.

Thus, at the last stage of the design process, the developerperforms prototype design verification based on programmable componentssuch as FPGAs. HES enables fast implementation of prototypeverification for IC designs in addition to providing advancedhardware-acceleration simulation.

The DVM provides specific API function libraries for the prototypeverification platform. Through these function libraries, engineers candevelop user-de- fined visual C/C++ programs and use them as visualman-machine interaction control interfaces for IC design prototypeverification.

Different IC design prototype verification platforms can be realizedusing HES. Through the daughter-board interface on the PCB, engineerscan connect the prototype design with other external devices such aslogical analysers or hardware excitation generators. Through these userdefined applications, the user can add the man-machine interactionmechanism into the prototype verification process.

Support Xilinx's ChipScope in-chip logical analysis tool. TheChipScope in-chip logical analysis tool enables debugging analysis oninternal signals of an FPGA chip. To use the Xilinx ChipScope tool,engineers must first insert the ChipScope core into the design codes.

The DVM can insert the ChipScope core into the design codesautomatically. After the prototype hardware is completed, the user canuse the JTAG interface and the ChipScope software tool to performdebugging analysis for the internal signals.

Wang Xiang is Section Technical Manager at Aldec Inc.

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