Embedded.com Tech Focus Newsletter (1-27-14): Dealing with embedded SoC design challenges - Embedded.com

Embedded.com Tech Focus Newsletter (1-27-14): Dealing with embedded SoC design challenges

January 27, 2014

Tales of embedded System-on-Chip design

For hands-on stories of how embedded hardware developers are solving difficult SoC, chip and board design problems, two excellent venues are Embedded.com and this week’s 2014 Designcon meeting of “chipheads.”

Designing low-power sequential circuits using clock gating

An efficient way to design low power sequential circuits with effective clock gating with the help of a multi-stage programmable Johnson counter.

Design Tip: Implementing an SoC with dependable 50% duty cycles

How to replace the conventional odd and even counter-based approach used in SoC circuit blocks with a dual-edge, counter-based, configurable frequency divider.

Benchmarking an ARM-based SoC using Dhrystone: A VFT perspective

The authors describe the development of a self-checking, result-signalling, tester pattern version of the popular Dhrystone benchmark.

Minimize leakage power in embedded SoC designs with Multi-Vt cells

The authors describe the use of a multithreshold voltage (Multi-Vt) flow technique that does not require embedded SoC architecture changes and allows a designer to decide when to use Low-Vt cells, which have better timing but higher leakage power, and when to use High-Vt cells which have lower leakage but worse timing.

Configurable dividers for SOC- and block-level clocking

Because SoCs comprise multiple blocks that need to run at different frequencies determined by multiple factors, designers need a configurable clock divider circuitry that can generate divided clocks from the master PLL/oscillator clock. This article illustrates the various implementations of configurable clock divider logic used in SoCs today and highlights their challenges, advantages or limitations.

Choosing an effective embedded SoC ASIC design strategy

This article details the difference in terms of runtimes, routing congestion, timing summary and utilization for an SoC ASIC design that is done using hierarchical methods vs. the same design using the flat approach

Reduce SoC power consumption without high-level circuit design tools

Tips and tricks to use early at the RTL coding stage in a system-on-chip design to reduce power consumption.

SOC DFT verification with static analysis

Verifying the connectivity of different IP blocks at the SOC level is usually done with functional simulation.

Reduce embedded SoC design cost & optimize IP integration

In this Product How-To, Cadence’s Neil Hand describes how the IP optimization techniques it has developed for use with its SuperSpeed USB 3.0 stack IP can aid in creation of cost effective SoC designs.

Building high performance interrupt responses into an embedded SoC design

Executing interrupt service routines using conventional techniques requires many clock cycles and limits the ability of the designer to verify the SoC IP (intellectual property) during silicon testing. Here is a technique to make that easier.

Powering Down: Enabling a Power Regression Flow for SoC Design

Current methods employed by designers for optimizing power are inefficient and unproductive, making it difficult to know when a design is fully power optimized. The solution: use power optimization tools that run in a regression mode to provide a feedback loop to designers and project management.



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