Embedded.com Tech Focus Newsletter (10-13-14): Signal integrity challenges in nextgen embedded designs

Today's high-speed communications designs with all their associated signal integrity issues could be tomorrow's challenges in mainstream embedded and mobile designs, so it is wise to keep an eye on how hardware chipheads are dealing with such problems.

Many mobile devices have multiple-input-multiple-output (MIMO) on-board antennas and present many challenges to signal integrity. Here is one approach to design that reduces noise significantly and makes comm links more immune to interference.

As the industry moves to adopt the MIPI Alliance’s M-PHY standard, designers are encountering some significant challenges related to oscilloscope measurements and, more specifically, probing.

In Part 1 of a two-part series, the authors delineate the various types of multiple input, multiple output (MIMO) antennae and provide some guidelines on how to make the right choices in a wireless base station design.

How to use a digital predistortion micromodule to build a fully integrated digital predistortion (DPD) reciver for use in cellular network base station designs.

ABCs of signal integrity – Part 1 explores some of the challenges of designing for signal integrity and possible solutions.

With the correct mix of PCIe clock generators and buffers, embedded systems developers can address the unique requirements of various applications.

The authors discuss the anomalies that can be introduced between the connecting wires on a high-density FPGA-based board and how to prevent them.

Why designers of printed circuit boards for nextgen ICs need to be savvy about package-on-package technology.

Analysis of both signal integrity and power integrity is vital to a successful high-speed digital design. Here's some perspective on why this is so and why in embedded designs the two need not be working a cross-purposes to one another.

The problems faced in dealing with clock jitter in FPGA-based high-speed communications interfaces such as SerDes and how external phase locked loops (PLLs) can be used to resolve them.

Jitter has become a significant percentage of a signal's interval, making it increasingly important to fully understand its types and sources. Most high-speed serial designs now use multiple lanes. Thus, crosstalk is nearly unavoidable.

On-Demand Webcast & Whitepaper: Java at Work in the Internet of Things Era

Managing the Chaos of Design Closure: How to regain control of your development schedule