There are many challenges to finding the right mix of memory storage and performance in networked designs, not only high-end routers and switches but in the more constrained and untethered environments of mobile devices, consumer wearables, and the Internet of Things.

NOR flash will make possible a new generation of wearable and Internet of Things devices if embedded developers are willing to rethink their basic assumptions about memory design.

An analysis of 45 flash based devices for use in solid state drives for mobile computing and data centers inidcates while SSDs are making substantial improvments relative to disks, cost is limiting their adoption in higher end applications.

Next-gen flash-memory features data-transfer rates as much as 10 times faster than currently available. Proper design strategies can help deliver reliable, high-performance systemsdespite increasing distortions in the data-carrying digital signals that can cause failures.

Storage performance on mobile devices, important for end-user experience, can be expected to grow in importance due to higher network throughput to mobile devices from such wireless technologies as 802.11n (600 Mbps peak) and 802.11ad (7 Gbps peak).

To NAND or NOR. That is the question. Different applications and functions should be handled with different types of flash memory.

Using a West Bridge interface embedded device developers can support multiple processor interfaces such as SRAM, ADMUX, SPI, and NAND as well as change NAND vendors with little to no software changes

While NOR and NAND flash memory will continue to evolve to higher densities and speeds, there are other non-volatile memory options that may address industry objectives for greater scalability, performance and efficiency.

A dynamic voltage scaling mechanism for multilevel NAND flash cells that adjusts thesupply voltages based on the type of operations to achieve up to 45% energy saving without the assistance of any special data encoding scheme.

Implementing an IPv6-based routing protocol over a wireless sensor network on an MSP430 with 7160 bytes of flash ROM and 370 bytes of RAM.

How to reduce NAND flash storage service time through the use of a RAM management scheme that improves flash translation layer performance by organizing address translation pages and data pages in RAM in a tree structure, through which it dynamically adapts to workloads.

How a new serial chip-to-chip interconnect protocol capable of 200-400 GB data rates can be used to eliminate throughput bottlenecks at the processor/external DDR memory interface.

Part 1 in a series on managing embedded system memory provides tips on improving software performance through the use of a variety of memory-oriented code and compiler optimization techniques.

On-Demand Webcast & Whitepaper: Java at Work in the Internet of Things Era