Embedded.com Tech Focus Newsletter (2-1-10): Designing with SerDes - Embedded.com

Embedded.com Tech Focus Newsletter (2-1-10): Designing with SerDes

Newsletter


02-01-2010

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EMBEDDED TECH FOCUS – DESIGNING WITH SERDES
As a technology journalist, I enjoy watching how particulardesigners and companies in the embedded sector develop solutions toproblems and designs that take advantage of market opportunities. Ialso get a chance to look at how the technology market place ingeneral, like any complex dynamic system, responds to external stimuli,challenges and opportunities.

In the technology environment sometimes the response to a challengeis to come up with something totally new. But more often the responseis what in biology is called “conversion of function” – rather thandevelop something totally new, an already existing function is adapted,added to, or used it in a different way to meet the need.

One example of this is SerDes, short forSerializer/Deserializer. All it consists of is a pair of functionalblocks which, in high speed communications links, compensates forlimited input/output. These blocks convert data between serial data andparallel interfaces in each direction. Although the term “SerDes” isgeneric, it is often used as a synonym for the Serial Gigabit Media Independent Interface.

The most recent imaginative use of SerDes is described in my Editor's Top Pick this week : Using SerDes infourth generation wireless infrastructure ,” by TI's AjinderSingh. Rather than add anything to it or adapt and integrate it intosome new advanced SoC, TI designers took one step back to enabledesigners to take two steps forward. In the article they describe adiscrete solution that provides designers with a great deal moreflexibility than any integrated solution could.

Some of the other recent examples of imaginative use of the SerDesfunction include: transformingvideo SerDes from a nightmare to a dream , modeling SerDes for usein board-level interconnects, how to use SerDes to deal with signaldegradation in multigigabit backplanes, copper SerDes as analternative to optical data links, adapting SerDes for use in the DDR-XAUImemory interface, and using SerDes in gigabitserial links over cable.

I had fun looking for these examples of the imaginative use ofSerDes in a variety of embedded designs. I hope you have as much funreading about them! (Embedded.comEditor Bernard Cole, bccole@acm.org )

  EDITOR'S TOP PICK by Bernard Cole, Embedded.com Editor
Using SerDes in Fourth Generation Wireless Infrastructure
As the network equipment infrastructure is built up for 4G there will be an demand for high serial data rates between the main control radio equipment and that in distributed base stations. Here is how to meet the high serial data rate by only ugrading the Serdes through the use of a discrete solution
  DESIGN ARTICLES
How to transform video SerDes from a nightmare to a dream
National Semiconductors' video SerDes solution involves a PHY chip with an interface to low-cost FPGAs and IP to implement all of the digital functionality in programmable logic.
How to use the IBIS BIRD104 to model advanced board-level SERDES I/O
How the IBIA BIRD104 proposal, with its C-language based API, can be used to model the SERDES I/O link requirements on advanced printed circuit board designs.
Extending your reach with Serdes
This brief tutorial deals with how to use Serdes to deal with signal degradation issues relating to multigigabit backplane, trace and cable distortion.
How to transmit a signal serially at 10 Gb/s
For system designers, it is imperative to understand the importance of clearly defining the system environment conditions. Otherwise, any incorrect assumptions made regarding the targeted system environment might invalidate the entire analysis and reduce the ability of the system to support serial 10 Gb/s across all targeted channels.
Gigabit SerDes: A key piece of the PON puzzle
Part 2 in a Texas Instruments Gigabit SerDes series on a solution to bandwidth constraints–SerDes-based PON–that now has a price tag that makes sense.
Gigabit Serdes: The Cure for Common Data Link Ailments
As systems from portable hand held devices to large networking equipment evolve, they will support more data throughput, be more power efficient, have increased reliability and, in most cases, support smaller form factors. All of these are key reasons that designers should consider SerDes-based data links as a key component for solving data link issues that they are likely to face.
Gigabit SerDes: Where SerDes copper gigabit links displace optical data links
The first of a two-part series by TI's Atul Patel: why copper cable-based short-haul gigabit links with gigabit serdes will likely be prefered due to cost, robustness and ease-of-implementation.
The Case for DDR-XAUI
Looking for a better understanding of DDR-XAUI compatibility interface for 10 Gigabit Ethernet? Ori Aruj from Dune Networks explains.
Implementing cost-effective gigabit serial links over cable
New technologies are readily found in integrated circuit devices such as gigabit serdes (Serializer/De-Serializers) that make implementing cable and backplane-based serial links much easier for the system designer. These advances in semiconductor technology are enabling systems designers to cost-effectively implement gigabit serial links.
Designing Serial ATA IP into your embedded storage device design
In designing the next generation terabyte level storage in many home electronics systems, serial ATA is the but interface of choice. But the quality,completeness and interoperability of this IP are key considerations when integrating it into an embedded SoC design.
Tutorial: the new JEDEC interface standard for data converters, Part 1 of 3
Understand the design implications of JESD204A for high-speed analog/digital and digital/analog converters
PRODUCT HOW-TO: Using an interface wrapper module to simplify implementing PCIe on FPGAs
Stephane Hauradou compares various approaches to implementing PCI Express on FPGAs to the PLDA EZDMA module interface wrapper to provide a simple and robust user interface with PCI Express hard IP.
  EDITOR'S NOTE: Continuing Your Education
ESC Silicon Valley is increasingly the place to get hands-on training. In the past, we told you how to develop your system, then you went back to your lab to make it work. Now, we're bringing that lab to you, giving you the hardware and software you need to design, develop, and debug your system. Find out more here. Note: Early-bird registration expires February 19th.

Finally, as the deployments of 3G Long Term Evolution (LTE) networks accelerate, engineers have their hands full developing and testing handsets to meet the extreme performance requirements these networks demand. Our online course, the Fundamentals of LTE Physical Layer and Test Requirements will take you through the LTE standard and show you how to set up to test user equipment using the latest test systems and techniques.

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