In his #include column in ESD Magazine this month, Ron Wilson asks: “Whatever became of the idea that we could define an embedded system in C, push the Compile button, and watch the tool spit out a complete hardware and software system design ?”
When VHDL and Verilog were introduced in the early 1980s, their impact on the hardware and software development communities was earth-shaking. Practically, it meant that the process of creating circuit layouts to direct fabrication of ICs could be further automated. It also meant that with Verilog/VHDL models, the boundary line between what was hardware and what was software was paper thin and the promise of pushbutton C/C++ software algorithms into IC designs could not be far away.
But reality happened and basic incompatibilities between the two environments has slowed progress. The advent of system-level modeling languages such as SystemC in the late 1990s, which deliberately mimics the operation and functionality of VHDL and Verilog, has done much to paper over the differences between the two.
ESD Magazine’s March cover feature on “Using SystemC to build a system-on-chip platform,” shows we are much further along than anyone dreamed in the 80s or 90s. But author James Aldis of TI points out it is hardly a pushbutton process and required a team of hardware and software developers working together to generate the carefully crafted System C, ESL and OCP-based performance models of the OMAP-2 platform and the devices based on it.
This is a topic we have been following on Embedded.com and within ESD magazine for almost a decade. Included below are some of the design articles, white papers, webinars, and online tutorials we have published recently on this topic, including my Editor’s Top Picks :
“Transitioning from C/C++ to SystemC in high level design”
“The war is over: C++ and SystemC coexist”
“Fit the hardware to the algorithm with SystemC ”
The dream of defining an embedded system in C or C++ and pushing the compile button to generate a complete hardware and software system design is a compelling one and not likely to go away. Join in the conversation online at the end of Ron Wilson’s column or James Aldis’s article. Better yet, if you have an idea for an article or a blog on the topic, contact me directly. (Embedded.com Editor Bernard Cole, email@example.com, 928-525-9087 )
Design How Tos
Using SystemC to build a system-on-chip platform
How Texas Instruments' designers used the SystemC hardware design language to do performance modeling when creating both the company's OMAP-2 platform and the devices based on it.
Transitioning from C/C++ to SystemC in high-level design
It's far easier to do architecture design in SystemC than it is to do it in C and C++. If co-designing hardware and software using high-level design methods, much of your work will be done in an architecture design phase in SystemC. Here's why.
The war is over: C++ and SystemC coexist in a single flow
Since its debut in 2004, the current generation of HLS tools has made tremendous progress in terms of both quality of results and wider applicability. The success of this technology cannot be denied: HLS is here to stay. However, as in other arenas of electronic design automation, a language war threatens to divide the user community, pitting C/C++ against SystemC.
A SystemC-Based RTOS Model for Multiprocessor Systems-on-Chips: Part 1 – Basic Concepts and Terminology
In this three part series, the authors describe an approach to modeling embedded applications represented as multithreaded applications executed on a multiprocessor platform running a number of, and possibly different, RTOSes
A SystemC/TLM based methodology for IP development and FPGA prototyping
This paper describes a methodology for IP development and System level platform development. The methodology in various stages of development keeps a homogeneous environment (including hardware and software) and permits the development to use similar environment and test benches.
Fit the hardware to the algorithm with SystemC models
Learn how to model DSP algorithms in SystemC without being a SystemC expert. These models facilitate hardware/software partitioning, and allow you to consider communication and memory architectures when designing your algorithm. These models also ease software development and hardware verification.
SystemC, transaction level modeling simplifies capture
IP companies have heralded a new age in platform-based design for years – ever since semiconductor integration capacity reached the point where entire systems could theoretically be integrated into a single die.
Designing hardware with C-based languages
With increasing design complexity and shortening time-to-market, hardware designers have sought to use higher levels of abstraction for both verification and design. For many hardware engineers, C-based languages (C/C++ or SystemC) have become a means to specify designs for verification, in addition to offering a starting point for implementation.
The 'what' and 'why' of transaction level modeling
Mentor Graphics' Bryan Bowyer covers the basics of transaction-level modeling, and shows how algorithmic synthesis can help with the signal processing portion of the design.
Programmable coprocessor generation from executable code: Part 1
In the first of a four part series, Skip Hovsmith with David Stewart & Richard Taylor compare traditional source level partitioning used in FPGAs to binary level hardware/software partitioning for optimizing of multicore or coprocessor designs.
C-based coprocessor design, part 1: SIMD architecture
Here's how CebaTech's C2R C-to-RTL compiler was used to implement a G723.1 and G729.A speech coding accelerator. The accelerator features configurable micro-architecture and instruction-set architecture.
Algorithmic synthesis improves designers' efficiency
Algorithmic synthesis moves the creation of application engines (algorithms on silicon) to a higher level of abstraction, giving significant time and cost savings.
Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1
In the first of a two part series, the OCP Debug Working Group describe work being done on the spec to reflect the needs of complex uniprocessor and multicore SoCs.
Utilizing OCP to design a high performance interconnect
The OCP standard support a split transaction bus protocol that enables designers to eliminate some of the latency due to data exchanges between cores in a SoC design.
CoWare releases SystemC modeling library source code
CoWare has released SystemC modeling library (SCML) source code and reuse methodology guidelines, a kit that openly extends SCML's standards-based approach to all IEEE 1666 SystemC-compatible tool environments.
SystemC synthesis tool adds improved C++ support
Celoxica Holdings said it has enhanced C++ coding support in its Agility Compiler high-level design tool, raising the level of design abstraction above SystemC for designers who need to boost productivity and for programmers less familiar with hardware design.
CoFluent bridges gap from UML to SystemC
French ESL company CoFluent Design (Nantes, France) claimed it has developed a methodology that combines the OMG's (Object Management Group) standards UML (Unified Modeling Language), SysML (System Modeling Language) and MARTE (Modeling and Analysis for Real-Time and Embedded Systems) profiles.
Spansion flash targets embedded applications
Spansion Inc. has expanded its family of NOR Flash memory devices to address applications in automotive, consumer electronics, and gaming.
Tool upgrade enables unit testing with hardware
The latest version of the Tessy tool for automated module/unit/integration testing of embedded software, now enables to incorporate hardware in unit and integration testing.
CoFluent, No Magic unveil UML to SystemC solution for multicore simulation
CoFluent Design (Nantes, France) and No Magic Inc. (Plano, Texas) announced they have combined MagicDraw UML Modeler and CoFluent Studio SystemC-based simulation environment to provide an integrated solution for executing use cases and analyzing the performance of multicore real-time embedded systems.
Mentor unveils TLM 2.0 design flow
EDA vendor Mentor Graphics announced a scalable design methodology based on transaction level model that, according to the company, allows a single model to be taken from design concept to implementation.