Embedded.com Tech Focus Newsletter (2-24-14): Phase-locked Loops - Embedded.com

Embedded.com Tech Focus Newsletter (2-24-14): Phase-locked Loops

February 24, 2014

The role of PLLs in 21st century embedded design

For an IC building block that came into being at about the same time as the microprocessor in the late 1960s and early 1970s, the “lowly” phase-locked loop has not done too badly.

Phase-locked loops in an IC-based clock distribution system

The hidden beauty of a PLL-based distribution system is that all the output clocks can be made to have a fixed-phase relationship to each other.

Phase-locked loops in an IC-based clock distribution system: Part 2 – Phase noise

The role of phase noise and phase jitter in an IC-based clock distribution system and how to minimize these effects.

Phase-locked loops in an IC-based clock distribution system – Part 3: Other sources of phase noise

The many sources of noise in phase-locked loops in IC-based clock distribution systems.

Dealing with PLL clock jitter in advanced processor designs: Part 1

In this first of a three part series, two engineers at Analog Devices, Inc. examine the sources of clock jitter in designs based on advanced RISC and DSP architectures, how to characterize your system for such problems and then how to resolve them.

Designing SoC-based PLLs require trade-offs

Phase-Locked loops are common circuits in SOCs (systems on chips). However, a “one-size-fits-all” PLL does not exist and such devices have have a range of frequency, power, area, performance, and functions that must be considered.

How to use an FPGA to test a PLL band calibration algorithm

Prototyping an ASIC design first on an FPGA is not only useful for verification but allows more room for algorithm experimentation.

Using programmable spread spectrum clock generators for EMI Reduction

To control EMI in consumer devices clock parameters like PLL charge pump current, VCO gain, and output drive strength, need to be programmable to improve system performance, reduce development time, and allows last minute changes.

Demystifying phase-locked loops

The Phase Locked Loop (PLL) is an indispensible component in modern electronic systems. For digital designers who still avoid its use because of its inherently analog nature and problematic implementation, hereis a different way to design a simple PLL.

Building a 1.5 volt 2.4 GHz CMOS PLL for Wireless LAN use

Designing a 1.5-V 2.4-GHz CMOS Phase Locked Loop for wireless LAN applications begins with the voltage controlled oscillator because the VCO is one of the most important elements in a PLL circuit.

Phase-locked loop design through the decades – Part 1

Predating the emergence of the modern semiconductor industry and today's submicron analog and digital CMOS processes, the venerable PLL remains a vital element in today's integrated circuit designs.

The basics of clock jitter in embedded system designs

With the increasing system data rates, timing jitter has become critical in system design, especially where system performance limit is determined by the system timing margin, making it important to understand the impact of timing jitter.


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Selecting Your Next Oscilloscope

Fundamentals of Understanding and Applying IGBTs

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