Embedded.com Tech Focus Newsletter (3-05-12): Tool up for HW-SW development at ESC DesignWest - Embedded.com

Embedded.com Tech Focus Newsletter (3-05-12): Tool up for HW-SW development at ESC DesignWest

Embedded Newsletter for 03-05-2012

» Click here to view online I » Forward to a friend I » Sign up for an EE Times Newsletter

Share this Newsletter:

facebook linkedin twitter digg

March 5, 2012

Tech Focus: Tool up for HW/SW development at ESC DesignWest

HIGHLIGHTS

Tracing requirements through to object-code verification

Troubleshooting real-time software issues using a logic analyzer

Fixing concurrency defects in multicore design


Editor's Note

Bernard Cole Bernard Cole
Site Editor
Embedded.com

With embedded systems an integral part of our lives and used in virtually every market segment, developers are under pressure to develop reliable and bug-free designs using every hardware and software tool and technique available. Of all the design articles, white papers, and webinars included in this issue of the newsletter, two articles featured in the March ESD Magazine do the best job of capturing the essence of the problems faced and the diverse methods that need to be used to solve them.

In “Troubleshooting real-time software issues using a logic analyzer , ” author David Stewart shows developers how to take a tool normally used to search out and resolve hardware design issues – the logic analyzer – and use it as a powerful software development tool.. “A debug tool only provides clues ,” he writes. “The better the clues, the faster the problem can be found, and thus the quicker it can be fixed. The logic analyzer takes more setup time than print statements or a symbolic debugger, but the quality and quantity of the clues can be significantly better .” If you enjoy his article you can get more of David Stewart at ESC Design West, March 26-28 , where he will be teaching four classes on the following topics: solving real problems (ESC-210), costly real-time development mistakes (ESC-223), remote troubleshooting with log files (ESC-313), and real-time Linux/Android or Windows CE (ESC-316).

In “Tracing requirements through to object-code verification , ” author Mark Pitchford addresses the difficult job of guaranteeing the reliability of not only the source code written by the developer, but the object code created by the compiler to run on a particular target MCU. To do this means not only making use of every tool and method available – debuggers, static analysis, software testing, and requirements-driven Agile design – but doing so in new and unfamiliar ways. To help you make your choices at ESC DesignWest there are four conference tracks relevant to these challenges: “Best Practices: HW and SW”; “New directions in software, processes and tools”; “Programming, Languages and Techniques”; and “Reasons to consider Agile Development”.

Columns on related topics this week on Embedded.com include: “Probing pointers” by Jack Ganssle,”Combining C's volatile and const keyword” by Michael Barr, and “Discriminated unions” by Dan Saks.


Design How-Tos

Troubleshooting real-time software issues using a logic analyzer

This logic analyzer technique is a power-tool for the embedded software engineer's toolbox.

A “How To” tutorial on logic analyzer basics for digital design

This tutorial provides an overview of logic analyzer basics; most logic analyzers are really two analyzers in one: a timing analyzer and a state analyzer.

That Was Tricky: The logic analyzer versus a DVM

This is a story about a race between two instruments; which one do you think will win?

Tracing requirements through to object-code verification

Verifying object code can mean the difference between success and failure, quality and crap. But skipping the step because a standard doesn't require it or because it theoretically eats into profits is a surprisingly common practice. The author postulates that this practice is not only shortsighted but no longer valid.

Using CMMI for software requirements testing in system design & development

Use the Capability Maturity Model Integration (CMMI) standard to improve software project processes, particularly requirements management and traceability.

Hardware/software design requirements planning: Part 1 – Laying the ground work

In this series of articles, Jeffrey O. Grady, author of “System Verification,” delineates the basics of requirements planning and analysis, an important tool for using Agile programming techniques to achieve better code quality and reliability in complex embedded systems software and hardware projects.

Requirements Management Reduces Software Defects and Improves Code Quality

Investment in software requirements management, equal to that made for design and coding, is necessary to secure a firm foundation on which to construct a successful project.

I don't need no stinkin' requirements!

How to manage an embedded systems project by designing it without requirements.

Using static code analysis for Agile software development

Since the goal of Agile development is to have working software early, source code analysis enables developers to analyze the quality and security of code from day one of coding ” one of the earliest points in the software development process

Using trace to solve the multicore system debug problem

In this article, Aaron Spear of VMware outlines current multicore development trends, explores the deficiencies in traditional software development tooling when applied to multicore systems, introducing the “Common Trace Format” (CTF), a coming standard for tracing multi-core systems over time.

Fixing concurrency defects in multicore design

There are compelling reasons to move to multicore processor designs, but doing so introduces the risk of concurrency defects in the software. Apparently innocent code can harbor nasty multithreading bugs that are notoriously difficult to diagnose and eliminate when they occur. Paul Anderson of GrammaTech offers methods to avoid these problems.


Embedded Systems Bookshelf

Excerpts

Embedded Books Reading Room
Bernard Cole's favorite links to book excerpts.

Reviews

Engineer's Bookshelf
Airport fiction blows. A look at books other engineers are reading and why you should read them, too. Recommend and write a review yourself. E-mail Brian Fuller.

Jack Ganssle's Bookshelf
A list of book reviews by Jack Ganssle, contributing technical editor of Embedded Systems Design and Embedded.com.

Max's Cool Beans
Clive “Max” Maxfield, the editor on Programmable Logic DesignLine, often writes about interesting books.


Products

The eyes reveal all: ultra-fast logic analyzer tackles DDR, other high-speed, multichannel challenges

Agilent U4154A AXIe-based unit captures 4 Gb/s; 68 channels, sees 100 ps/100mV eyes; adds advanced probe sets

Logic analyzer option cut costs for data capture

Agilent Technologies Inc. has added a lower-priced entry-level 1.4-Gb/sec state mode option for its U4154A logic analyser.

Logic analyzer / signal generator for $99

The ScanaLogic2 from Saelig Company Inc. is a PC-based 4-channel logic analyzer and digital signal generator. It provides the ability to generate digital signals, while recording the response on other channels and computer-independent performance and timings, with a quartz-accurate maximum sampling rate of 20MSa/s.

Logic protocol analyzer enhanced for PCIe

Additional software capabilities for the Tektronix TLA7SA08 and TLA7SA16 Logic Protocol Analyzer Modules provide support for PCI Express (PCIe) 3.0. The additions include a Bird's Eye View (BEV) to help engineers visualize and investigate difficult flow control problems along with one-click calibration and auto configuration.

DDR2 test option for TLA6000 logic analyzers

Tektronix Inc.,has developed a complete DDR2 protocol debug and validation solution for the TLA6000 logic analyzers which provides everything needed to validate and debug the operation of memory sub-systems in designs.

Visure Solutions announces test management extension for IRQA

Visure Solutions has integrated test management into its IRQA requirements engineering solution.

New version of PLS Universal Debug Engine simplifies multicore control and debugging

PLS Universal Debug Engine (UDE) 3.2 features new functions for multicore control, unique visualization capabilities at system level, and dedicated support for a wide range of the latest 32-bit SoCs from different manufacturers.

Don't Miss the 2012 UBM ACE Awards!

Two powerhouse awards programs–better together.

New this year, EE Times' ACE (Annual Creativity in Electronics) Awards and EDN's Innovation Awards are joining forces to honor the people and companies — the creators — behind the technologies and products that are changing the world of electronics and shaping the way we work, live, and play. The result: the 2012 UBM Electronics ACE Awards taking place on March 27, 2012 during DESIGN West Join us as we celebrate the industries best of the best.
Order your tickets today!


Commentary

Probing pointers

The wrong probe can cause your circuit to fail or even physically destroy components. Here are some of the issues.

Opinion: Your logic analyzer can probe those forgotten signals!

Logic analysis is a powerful tool. However, the most powerful logic analyzer is useless without a sound probing connection to a system under test. If you approach the problem carefully, you'll find that you can even probe those “forgotten” signals. From eeProductCenter's Test and Measurement section, Agilent Technologies' engineers offer these pointers.

Scoping out new scopes

After pressing, twisting, and pushing knobs, Jack Ganssle likes what he sees in a new mixed-signal scope series from Agilent Technologies.

Sorting out the confusion about using multicore

While many embedded designs use multiple microprocessors in a specific design, few developers, except for apps in consumer and networking – are willing to integrate them all into a multicore SoC. At ESC DesignWest, classes will address the achitectural and software stumbling blocks and provide guidelines on how to make the transition.

Getting a headstart on embedding Android

Here are some resources for embedding Android in your design from around the web and at the upcoming ESC DesignWest conference in San Jose, Ca.

Safety threats: from satellites to pods in your pocket

DARPA's new High-Assurance Cyber Military Systems (HACMS) is looking for a few good synthesizers capable of machine-checkable proofs.


Sponsored White Papers

window.NREUM||(NREUM={});NREUM.info={"beacon":"bam.nr-data.net","licenseKey":"80caaa83e0","applicationID":"197311801","transactionName":"NgMGZREHV0JUAkEMDQ9JJVIXD1ZfGhJcCwUNAw==","queueTime":0,"applicationTime":267,"atts":"GkQRE1kdRB0XABdfGRwb","errorBeacon":"bam.nr-data.net","agent":""}

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.