Tech Focus: The basics of Kalman filters
Can you give me an estimate?
Introduction to Kalman Filtering
Using nonlinear Kalman filtering to estimate signals
The topic of this week’s Embedded Tech Focus newsletter – Kalman filters – came about as a result of a telephone conversation. The developer I was talking to commented about all the attention I had given in recent newsletters to 555 timers and watchdog circuits as important embedded hardware building blocks.
He pointed out that there are several circuits and algorithms that were just as widely used, such as Kalman Filters. That threw me for a loop, for while widely used in their fully expressed form in many military and aerospace applications, I did not think they could be called ubiquitous. But he reminded me that the simplest form of a Kalman filter is the Phased-Locked Loop (PLL), which is used everywhere.
There is a treasure trove of articles and white papers about designing with Kalman filters and PLLs on Embedded.com, as well as on their use in some surprising venues. I have linked to some of these below. But first you should read “Can you give me an estimate?” a recent column by Jack Crenshaw on Kalman filters and his use of least squares fit calculations.
He has long experience in designing with Kalman Filters in the space program, and I have included several previous columns by him on that topic. His columns are sometimes tough going, but it’s worth the effort because at the end you will have learned something valuable. Enjoy?
Design How Tos
Originally developed for use in spacecraft navigation, the Kalman filter turns out to be useful for many applications. It is mainly used to estimate system states that can only be observed indirectly or inaccurately by the system itself.
Using nonlinear Kalman filtering to estimate signals
First developed to aid in navigating spacecraft during the Apollo missions, the nonlinear or extended Kalman filter is still the workhorse of signal estimation. Expert Dan Simon introduces us to the concept of nonlinear Kalman filtering, explains the math, and provides Matlab simulation code.
Introduction to Minimax Filtering
Limitations of Kalman filtering gave rise to H∞ filtering, also known as minimax filtering. Minimax filtering minimizes the “worst-case” estimation error. More precisely, the minimax filter minimizes the maximum singular value of the transfer function from the noise to the estimation error. Innovatia Software's Dan Simon provides an introduction to minimax filtering.
Tutorial on PLLs: Part 1
Have to design with a PLL? This two-part series provides you with the basics and theories needed to implement a PLL in a communication design.
Jitter attenuation 101: How do you pick the right PLL bandwidth?
Understand the factors which affect phase-lock loop jitter and the interaction between them
How to use an FPGA to test a PLL band calibration algorithm
Prototyping an ASIC design first on an FPGA is not only useful for verification but allows more room for algorithm experimentation.
Unlock and Load: Characterizing Today's PLLs
Real-time spectrum analysis provides a valuable means to characterize, measure, and view the behavior of PLLs used in communication designs.
Understanding the basics of PLL frequency synthesis
The critical parameters of a PLL design interact and must be considered individually as well as collectively
Back to the future: Manchester encoding – Part 1
When commercial options fail, try using Manchester encoding and other time-tested protocols in low-cost, low bit-rate serial communications.
Harness speed, performance, signal integrity, and low current advantages of 65nm QDR family SRAMs
QDR devices based on 65 nm technology provide the ability to achieve high performance and bandwidth with few changes to existing boards in networking applications. Here's how.
Implementing Embedded Speed Control for Brushless DC Motors: Part 1
The first in a six part tutorial on BLDC motor control fundamentals and implementation using 120-degree trapezoidal control with and without sensors and 180-degree sine wave modulation and V/f open-loop and closed-loop control with sensors.
MicroBlaze hosts mobile multisensor navigation system
Researchers used Xilinx's soft-core processor to develop an integrated navigation solution that works in places where GPS doesn't.
ESC Silicon Valley May 2–5 2011
Spring is here and ESC Silicon Valley 2011 opens just five weeks from today, on Monday, May 2, 2011, at the McEnery Convention Center in San Jose, California. This year's event promises to be both entertaining and educational, with a keynote by Apple co-founder (and self-proclaimed embedded systems designer) Steve Wozniak as well as technical training from these popular speakers:
–Jack Ganssle on Managing Firmware Projects and Mars Ate My Spacecraft
–W illiam Gatliff jumpstarts Android and Embedded Linux
–James Grenning demonstrates Agile and Test Driven Development
–Dan Saks debunks C++ Myths and shows how to Refactor C into C++
–Check out the full program.
This year ESC is also co-located with the Multicore Expo and TI Technology Day .
The early registration discount has been extended until Friday, April 8th for 4 day and all Access passes.
We are rolling back the Early Bird registration discount plus your 20% Alumni discount for one week only until Friday, April 8th for 4 day and all Access passes—up to $1,039 savings*.
Use Promo Code: EMBNL to get access to Early Bird pricing on 4 Day and All Access passes plus save an additional 20% and be entered to win a free seat at Embedded Software Boot Camp or one of twenty copies of the Embedded C Coding Standard book.
Invite your colleagues! Group discounts are available.
*$1,039 savings off the on-site price for an All Access Pass. Includes 20% Promo and Early Bird pricing discount if registration is complete by April 8th, 2011.
ESC – Green Hills integrates DoubleCheck static code analyzer with MULTI IDE
Green Hills Software, Inc., is now providing its user-based static code analyzer, DoubleCheck as a standard feature with its MULTI Professional tool suite for multicore development and debugger solutions. The integration is intended to increase developer productivity and code quality while enabling better management and control of code complexity and the overall coding process.
Static analysis tool maps code's 'DNA'
Coverity Inc. says the new release of its Prevent static code-analysis software embodies a new approach to “software mapping” that finds more bugs in embedded and enterprise software than previous technologies. The Prevent Software Quality System (SQS) also includes new defect- tracking capabilities and Java support.
Automating static timing analysis process
EMA Design Automation announced TimingDesigner 9.25 with enhanced Automerge functionality, which the company claims, dramatically decreases the time required for performing interface timing analysis.
ESC NEWS: GrammaTech offers CodeSonar Enterprise with Web-based Defect-Management System
New web-based tool analyzes C/C++ code to find complex programming bugs.
LDRA tool suite delivers ISO 26262 compliance for automakers
LDRA tool suite now supports the current implementation of ISO/DIS 26262, a functional safety standard for road vehicles.
News & Analysis
ADI, Altera collaborate on wireless infrastructure platform
Analog Devices announced a high-performance development platform for wireless infrastructure equipment designers to quickly evaluate systems using digital pre-distortion techniques in multi-carrier cellular base stations.
ADI – Xilinx collaboration streamlines base station design
Analog Devices Inc. has collaborated with Xilinx Inc to introduce a radio architecture development platform that helps multi-carrier cellular base station manufacturers reduce engineering resources and improve time to market.
Any-frequency clock generator debuts
Analog/mixed-signal chip maker Silicon Laboratories introduced a clock generator that synthesizes any eight frequencies without the need for separate phased-locked loops.
PLL frequency synthesizer portfolio claims industry's lowest low phase noise in satellite applications
Peregrine Semiconductor Corporation has anounced the UltraCMOS PE97022 and PE97042 phase locked loop (PLL) frequency synthesizers for satellite payload designs.
Torex : PLL clock generator has built-in divider/multiplier
The XC25BS8 series of PLL clock generator ICs with built-in crystal oscillator circuit, divider circuit and multiplier PLL circuit is suitable for low voltage and battery-powered applications of between 2.5 and 5.5 V.