Embedded.com Tech Focus Newsletter (4-11-11): Multicore - Embedded.com

Embedded.com Tech Focus Newsletter (4-11-11): Multicore

Embedded Newsletter for 04-11-11

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April 11, 2011

Tech Focus: Kick the tires on multicore designs at ESC 2011

HIGHLIGHTS

Analyzing multithreaded applications—Identifying performance bottlenecks on multicore systems

Using trace to solve the multicore system debug problem

Non-intrusive debug & performance optimization for multicore systems

Trip over threads to trap multicore bugs

Is lock-free programming practical for multicore?


Editor's Note

Bernard Cole Bernard Cole
Site Editor
Embedded.com

The new 2011 Embedded Market Study indicates that the developers surveyed are still cautious and in the kicking-the-tires stage when it comes to using multicore SoC architectures in their designs. Similar to the results in the previous three years, about 85 percent say they use multiple single core MCUs in their current projects and only about 15 percent are using multiple cores on the same chip, and then only with traditional C and C++ languages and tools.

Similarly, on Embedded.com, month-to-month site traffic statistics indicate traditional single processor design topics are still the most popular. But nevertheless the articles that most often grab your interest and drive traffic on a daily or weekly basis are those that tell you about effective multicore kicking-the-tires tools and techniques for debugging, testing, benchmarking, and performance analysis. Go figure. Some of the most popular recently have been:

Using trace to solve the multicore system debug problem
Non-intrusive multicore debug & performance optimization
Identifying performance bottlenecks on multicore systems
Debugging real-time multiprocessor systems

If you need more help with multicore tire-kicking, you’re in luck. At the Multicore Expo to be held in conjunction with the 2011 Spring ESC in San Jose, Ca., May 2-4, about a dozen of the 40 presented papers and classes will be on multicore evaluation, testing and analysis including:

SW Debug on Heterogeneous Multicore Virtual Prototypes (ME889)
Invaluable Techniques for Multicore Debugging (ME841)
Using Multicore to Benchmark Performance (ME582)
Make your multicore program fail again (ME820)
Analysis & Quantification of Multicore performance (ME851)

Important note: Starting April 18, the Embedded.com newsletters will arrive in your mailbox about 10 -12 hours later. Depending on where you are on the globe, you can expect to see them in your email on Mondays and Thursdays.


Design How Tos

Is lock-free programming practical for multicore?

In a multicore environment, you can do resource sharing efficiently without locks, but there are some caveats.

Multi-Core — A New Challenge for Debugging

Development of complex systems with powerful hardware on one side and ambitious applications on the other side, benefits from on system-spanning on-chip support for debugging.

Debugging real-time multiprocessor systems: Part 1

In this first of a two part series, Jakob Engblom of Virtutech deals with the challenges of parallel programming and debugging in an embedded, real-time multiprocessing environment.

Debugging a Shared Memory Problem in a multi-core design with virtual hardware

This article demonstrates how a virtual platform can be used to debug a shared memory problem in a multi-core design.

CoreMark: A realistic way to benchmark CPU performance

The CoreMark CPU benchmark maximizes simplicity and efficacy.

Multi-core analysis made easy with the Nexus 5001 debug spec

If you are looking for a nextgen follow on to the JTAG debug interface for your multicore-based design, take a look at the Nexus 5001 debug spec, which supports the use of high bandwidth interfaces to efficiently transport data between the silicon targets and debug tools.

Putting multicore processing in context: Part One

In Part One in a series on multicore design, the author reviews a little of the history of multiprocessing and looks at key parameters in a design and how to assess if a design needs multiple processors and if it does, how to do it.

Multicore's “fourth semaphore”: multiple reader – writer lock”

According to David Kalinsky, as embedded systems move to multi-cores, traditional semaphores have been joined by a fourth kind: the multiple reader – writer lock. He explains how the new semaphore works, and in which multi-core apps it is best used.

Defining standard Debug Interface Socket requirements for OCP-Compliant multicore SoCs: Part 1

In the first of a two part series, the OCP Debug Working Group describe work being done on the spec to reflect the needs of complex uniprocessor and multicore SoCs.

Tackling memory allocation in multicore and multithreaded applications

Embedded database experts from McObject describe how to build a custom memory manager to avoid the locking conflicts that often occur in multithreaded or multicore designs with two or more processors.

Applying the fundamentals of parallel programming to multiprocessor designs: Part 1

In this two part article, Shameem Akhter and Jason Roberts of Intel provide details on using threads in a parallel programming environment to enable multiple operations to proceed simultaneously. This week: Breaking up tasks.


It's less than a month now until ESC Silicon Valley 2011 at the McEnery Convention Center in San Jose, California and we are
getting fired up about all the great hands-on educational opportunities.
We are especially excited about the just-announced Beer and Boards training available for All Access pass holders!
Pick one of the development kits to take home:
•   Texas Instruments CC2540DK-MINI Development Kit
•   XL_STAR complete MCU development environment
•   Avnet Spartan-6 LX9 MicroBoard

Info on each board is here:
http://esc.eetimes.com/siliconvalley/boards_beer?cid=EET_BNBPV

Then attend a gathering and meet with the board's designers, where you will learn about the kit and share a few beers.
Development kit supplies are only available to All Access Pass Holders – so make sure you register now, quanitites are limited.

Register Online: https://esc.embedded.com/sv/2011?cid=EET_BNBPV

Here are some additional the other hands-on training courses at this years conference:
•   Hands-on TCP/IP Half-Day Tutorial – http://schedule.esc-sv09.techinsightsevents.com/session/88?cid=EET_BNBPV
•   Capacitive Touch Workshop  – http://schedule.esc-sv09.techinsightsevents.com/session/17?cid=EET_BNBPV
•   Hands-on with USB/I2C/SPI Protocol – http://schedule.esc-sv09.techinsightsevents.com/session/26?cid=EET_BNBPV
•   Check out the full program – http://esc.eetimes.com/siliconvalley/conference
•     You can also interact with industry experts like Jack Ganssle at Shop Talks .

Use Promo Code: “Beer&Boards” for and additional 20% discount* and be entered to win a free seat
at Embedded Software Boot Camp or one of twenty copies of the Embedded C Coding Standard book.
Register Online:  https://esc.embedded.com/sv/2011?cid=EET_BNBPV


Products

Multicore MCUs target ADAS applications

A new range of 32-bit MCU family has been designed to make advanced driver assistance systems more affordable for a broad range of vehicles. It could help promote safety features, such as blind-spot detection, lane-departure warning systems, side view assistance and adaptive headlights.

Lauterbach integrates support for SYSGO's PikeOS into TRACE32 debug

The newest version of SYSGO's real-time operating system PikeOS is now integrated with Lauterbach's TRACE32 Debugger tools. PikeOS awareness is included in all new releases of the TRACE32 software for PowerPC; other architectures will follow soon.

TenAsys debuts multi-core, multiplatform network RTOS

TenAsys INtime Distributed RTOS delivers scalable performance without requiring software changes.

JamaicaVM 6 is now available for multicore systems

A new multiprocessor version of the JamaicaVM hard realtime Java runtime environment has been introduced by the aicas group, and will be demonstrated at the Embedded World conference in Nuremberg Germany from 1-3 March 2011. The new version is based on the JamaicaVM 6 product, which supports the J2SE Java 6 standard classes.

Synopsys unveils multicore optimization technology

Embedded in the company's Platform Architect, Synopsys Inc. (Mountain View, Calif.) said the Multicore Optimization Technology is meant for performance analysis and early definition of multicore system architectures in SystemC.

EVE enhances ZeBu debugging capabilities

EVE SA (Palaiseau, France) has developed superior debugging capabilities for its ZeBu emulation platform so that designers can quickly and easily generate design waveforms.


News & Analysis

Multicore programmers must 'think different'

Engineers need to think differently to be successful in the transition to multicore programming, according to UT professor Yale Patt in online conference this week.

Virtual debug interface speeds software development

ARM has introduced the VSTREAM virtual debug interface to provide a virtual link that connects software debuggers to hardware assisted verification systems to enable more efficient software development in the early stages of system design.

Mentor, Lauterbach team on embedded software debug

Mentor Graphics Corp. said it has combined its Veloce dual-mode accelerator/emulator with the integrated debug and development tools from Lauterbach GmbH. The purpose is to deliver a hardware-accelerated, software-development and debug platform for the verification of SoCs and embedded systems.

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