The 2014 Design Automation Conference in San Francisco, Ca., June 1 to 5, offers a clear and detailed view of the tough challenges ahead in embedded hardware and software development relating to low power, multicore design, sensors , automotive and industrial applications.

The use of a 2.5D system to integrate basic SoC functional blocks can eliminate much of the routing congestion that results when sending signals back and forth between cooperating elements.

How to boot Linux on the ARM Cortex-A15 using virtual prototyping to build fast, functional software models of a system that can execute production code.

Imagination's Peter McGuinness recounts his company's experience in porting disparate applications to run delegated to the GPU and reports on lessons learned.

In this Product How-To article, the Cadence authors describe how to use the company’s Verification IP solutions framework to implement ARM’s AMBA 4 Coherency Extensions (ACE) in embedded SoCs

The authors describe the development of a self-checking, result-signalling, tester pattern version of the popular Dhrystone benchmark.

How to deal with the challenges of power aware verification in SoCs and use IEEE 1801-2009 Unified Power Format to define power management architecture for verifying a power-managed ARM-based design.

A programmable many-core platform containing 64 digital signal processor cores routed in a hierarchical network tor biomedical signal processing applications.A programmable many-core platform containing 64 digital signal processor cores routed in a hierarchical network tor biomedical signal processing applications.

A software-defined radio application for 4G mobile devices that uses a homogeneous processor array incorporating smart modem processors (SMEP) interconnected with a Network-on-Chip.

How standards based programming models like OpenCL and OpenMP make it possible for embedded programmers to write their applications in the C language, and still take advantage of the offload capability of additional accelerators and efficiently task heterogeneous cores.

A lightweight implementation in VHDL that enables explicit and direct use of multiple core instances in an FPGA based embedded design.

A processor designed specifically for mixed criticality systems that allows each task to make trade-offs between hardware-based isolation and efficient processor utilization.