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Tech Focus: Is EDA stuck between a rock & a soft(ware) place?
HIGHLIGHTS
Down & dirty with HW/SW co-design: Part 1 – Reviewing the fundamentals.
HW/SW co-verification basics: Part 1 – Determining what & how to verify
Breathing life into hardware and software codesign
Editor's Note
The quandary facing those with a seemingly irresolvable dilemma is often described as being caught “between a rock and a hard place .” However, the dilemma facing IC designers and the suppliers of their electronic design automation (EDA) hardware tools is probably better described as being caught “between a rock and a soft(ware) place .”
IC developers have pushed transistor geometries down to the tens of nanometers to increase the gate functionality of their designs. This has allowed the construction of impressive multicore-based system-on-chip designs that increase functionality beyond what anyone could even imagine just a few years ago. But just as the internal combustion engine requires fuel to power it, complex multiprocessor SoC designs need software to run them – lots of it – and it must be developed in close coordination with the evolving hardware design.
This fact came home – again – to roost, at the Design Automation Conference (DAC) this past week and the Embedded Systems Conference in May. In a DAC video , EDN/ESD editor Ron Wilson captures the essence of the situation facing IC designers.
At both shows numerous panels and classes were devoted to the topic. At ESC, EDA vendor Cadence showed its System Development Suite for hardware/software integration, and at DAC, competitor Mentor Graphcs touted its new Common Embedded Software Development . This is not the first time such efforts have been attempted, as evidenced in the design articles included here. But will it take this time? Will a truly useable integrated hardware/software framework emerge?
In addition to “Down and dirty with hardware/software design,” the first in a series of articles this week by Wayne Wolf, other articles I’ve included as my Editor’s To Picks on this vital topic include:
HW/SW co-verification basics
Breathing life into hardware/software codesign
Approaches to accelerated HW/SW coverification.
Design How Tos
Down & dirty with HW/SW co-design: Part 1 – Reviewing the fundamentals.
In a four part series, Wayne Wolf looks at the total hardware/software co-design process & the methodologies embedded designers must learn, or relearn as the two disparate methodologies begin to merge. Part 1: Reviewing the fundamentals
HW/SW co-verification basics: Part 1 – Determining what & how to verify
In this four part series, Jason Andrews details the importance of co-verification of both hardware and software in embedded system design and provides details on the various ways to achieve this. Part 1: Determining what and how to verify.
It's not just about hardware anymore
Chip designers need to prove that software works, and do so quickly. A hardware/ software emulator may be the only way that a team can demonstrate that they've done a good and thorough job in a timeframe consistent with today's demanding product cycles.
Is software the new hardware?
Building an embedded product is a complex undertaking, involving highly intertwined hardware and software components and thousands of individual design decisions. The pressure to deliver a product to market quickly makes complexity still more difficult to manage, because design trade-offs and alternatives can't always be properly tested and evaluated.
Address system-level HW/SW design tasks with Electronic System Level tools
To keep track of design size and complexity, designers are now looking for the next breakthrough in design productivity, implementation and verification. One answer may be electronic system level design.
Breathing life into hardware and software codesign
From theory to practice, this article comes from one who's done it all. Hardware/software codesign is the goal of every (well, most) embedded systems designers. To have the hardware and the software both spring forth from the same designer's pen is enough to make any manager glad.
A Simple New Approach to Hardware Software Co-Verification
Ernst Zwingenberger of El Camino GmbH details how Coverage-driven verification can be performed on both hardware and software in an System-on-Chip being designed for use in an HDTV application.
Validate hardware/software for nextgen mobile/consumer apps using software-on-chip system development tools
A new breed of mobile smartphone platforms and embedded consumer devices is now emerging requiring applications software and extensions that go far beyond just enabling user-level software customization
Leveraging virtual hardware platforms for embedded software validation
A hybrid approach to configuring a virtual hardware platform enables developers to explore all facets of the system long before it's built.
How effective use of ESL tools can increase your HW/SW system design productivity
The use of Electronic System Level tools, complemented by techniques such as Sequential Logic Equivalence Checking (SLEC), will significantly improve system design productivity especially as designs move to geometries below 90 nanometers.
Functional TLM simplifies heterogeneous multiprocessor software development
To keep up with growing computational requirements, throughput and integrated system features of today's multiprocessor architectures, functional transaction-level modeling is a needed tool in the creation of software models that mirror the hardware requirements.
Using unified modeling methods to reduce embedded hardware/software development
Exploding system development costs and shrinking schedules are driving the industry to a new level of abstraction – transaction level modeling (TLM)
Embedded Systems Bookshelf
Excerpts
Embedded Books Reading Room
Bernard Cole's favorite links to book excerpts.
Reviews
Engineer's Bookshelf
Airport fiction blows. A look at books other engineers are reading and why you should read them, too. Recommend and write a review yourself. E-mail Brian Fuller.
Jack Ganssle's Bookshelf
A list of book reviews by Jack Ganssle, contributing technical editor of Embedded Systems Design and Embedded.com.
Max's Cool Beans
Clive “Max” Maxfield, the editor on Programmable Logic DesignLine, often writes about interesting books.
Products
Mentor extends embedded design into ESL
Common Embedded Software Development Platform integrates electronic system level (ESL) capabilities into CodeSourcery tools to support development from virtual prototypes to hardware emulation and boards.
Mentor's TLM Synthesis links virtual prototyping and hardware implementation
Mentor Graphics has announced that its Catapult C high-level synthesis (HLS) tool now supports the synthesis of transaction level models (TLMs).
Mentor unveils TLM 2.0 design flow
EDA vendor Mentor Graphics announced a scalable design methodology based on transaction level model that, according to the company, allows a single model to be taken from design concept to implementation.
CoFluent bridges gap from UML to SystemC
French ESL company CoFluent Design (Nantes, France) claimed it has developed a methodology that combines the OMG's (Object Management Group) standards UML (Unified Modeling Language), SysML (System Modeling Language) and MARTE (Modeling and Analysis for Real-Time and Embedded Systems) profiles.
Systems-on-chip: Library bolsters SystemC
Filling what it sees as missing capabilities in the SystemC verification environment, Jeda Technologies Inc. this week will introduce NSCv, a C++ verification class library for SystemC.
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