Embedded.com Tech Focus Newsletter (6-4-12): Getting serious about embedded design at DAC 2012 - Embedded.com

Embedded.com Tech Focus Newsletter (6-4-12): Getting serious about embedded design at DAC 2012

Embedded Newsletter for 06-04-2012

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June 4, 2012

Tech Focus: Getting serious about embedded design at DAC 2012


Expanding emulation's reach with virtual devices

Using emulation to debug software and hardware at the same time

HW/SW co-verification basics: Part 1 – Determining what & how to verify

Editor's Note

Bernard Cole Bernard Cole
Site Editor

For more than a decade embedded systems developers have looked with hope and optimism at the emergence of hardware description languages such as C++ derived System C ,C-derived Verilog, Ada-derived VHDL , and the various EDA tools for simplifying hardware/software co-design, co-verification, and emulation. Typical of that early optimism is “The architecture exploration process , ” written by Lloyd Pople in 2000. That optimism has continued in more recent design articles, white papers, and webinars on these topics, of which my Editor's Top Picks are:

Use emulation to debug SW/HW at the same time by EVE-USA's Donald Cramb
Expand emulation's reach with virtual devices by Mentor Graphics' Jim Kenney
HW/SW co-verification basics, a four part series by Jason Andrews

That synergy between embedded systems software developers, SoC chip designers, and EDA vendors is front and center this week at the 2012 Design Automation Conference in San Francisco. In addition to Rolf Ernst's Perspectives Presentation on “Embedded systems – the neural backbone of society ,” my Editor's DAC Recommendations are:

Applications of virtual platforms
Real world heterogeneous multicore
It's the software, stupid: truth or myth?
Parallelization and software development
Native embedded software development solutions
Software & firmware engineering for complex SoCs
Optimizing embedded software for high performance & reliability

If you are not attending DAC this year, be sure to follow the action online at the EE Times Live Stream and view the videos of Brian Fuller interviewing industry experts on these and other topics.

Design How-Tos

Expanding emulation's reach with virtual devices

In this Product How-to design article, Jim Kenney discusses the increasing importance of virtual device emulation in hardware/software co-design, using a Veloce customer's experience with the Mentor Graphics VirtuaLAB's ability to generate Ethernet traffic that exercises an edge router chip.

Using emulation to debug software and hardware at the same time

For developers involved in creating an SoC for their embedded designs where it's essential to run both software and hardware debug together, here's a step by step guide to using an emulator make sure the system is truly ready to be committed to silicon.

HW/SW co-verification basics: Part 1 – Determining what & how to verify

In this four part series, Jason Andrews details the importance of co-verification of both hardware and software in embedded system design and provides details on the various ways to achieve this. Part 1: Determining what and how to verify.

It's not just about hardware anymore

Chip designers need to prove that software works, and do so quickly. A hardware/ software emulator may be the only way that a team can demonstrate that they've done a good and thorough job in a timeframe consistent with today's demanding product cycles.

Down & dirty with HW/SW co-design: Part 1 – Reviewing the fundamentals.

In a four part series, Wayne Wolf looks at the total hardware/software co-design process & the methodologies embedded designers must learn, or relearn as the two disparate methodologies begin to merge. Part 1: Reviewing the fundamentals

How effective use of ESL tools can increase your HW/SW system design productivity

The use of Electronic System Level tools, complemented by techniques such as Sequential Logic Equivalence Checking (SLEC), will significantly improve system design productivity especially as designs move to geometries below 90 nanometers.

How to make virtual prototyping better than designing with hardware: Part 1

This series of articles analyzes the benefits of virtual prototyping in embedded systems design with a particular focus on its usefulness after physical prototype is available for software, systems, and verification engineers. Part 1: The use cases for virtual prototyping.

System level software centric power debugging using virtual prototypes

Achim Nohl of Synopsys describes how Virtual Prototypes (VPs) provide all the necessary elements for a debug solution that can spot and remove power related defects from software.

Dealing with the challenges of integrating hardware and software verification

Stan Smith explores challenges and solutions necessary to achieve the closer integration of software development and validation with silicon design and verification.

Breathing life into hardware and software codesign

From theory to practice, this article comes from one who's done it all. Hardware/software codesign is the goal of every (well, most) embedded systems designers. To have the hardware and the software both spring forth from the same designer's pen is enough to make any manager glad.

Achieving first day multicore SoC software success

A well designed virtual platform is an integrated ecosystem that makes it easy to create or download models that allow design teams to combine them in ways that can initially be run fast and then switched to full accuracy to make precise measurements or to investigate low-level performance issues.

A Simple New Approach to Hardware Software Co-Verification

Ernst Zwingenberger of El Camino GmbH details how Coverage-driven verification can be performed on both hardware and software in an System-on-Chip being designed for use in an HDTV application.

Using a processor-driven test bench for functional verification of embedded SoCs

Jim Kenney of Mentor Graphics describes the usefulness of processor-driven tests to drive test vectors into a design via the processor bus and compares several different methods.

Product How-To On: Exploring Multicore Power Management with Modeling and Simulation

How to use Mirabilis Design's VisualSim to model and provide accurate results and the task/power efficiency metrics for multicore designs running at different clock speeds with completely different power algorithms.

2012 Embedded Market Survey webinar

UBM Electronics' 17th annual survey of embedded systems designers worldwide shows trends in software and hardware usage. The 2012 Embedded Market Survey also looks at languages, productivity, and the challenges design teams rank as most important. A webinar on Friday April 20 will examine the results from over 1,700 respondents from across the embedded industry, the dataset enables a deep analysis to track key changes in this important electronics industry segment. There will also be the opportunity to ask questions online. To register click here .


IP being made more accessible

For people who wish to try before buying, the whole notion of reference designs and the implementation of them is a great idea…

ARM POPs for better designs

ARM extends their Processor Optimization Packs to help customers get better design solutions with lower levels of risk…

Emulation market growing. Mentor ups the ante.

The emulation market is growing and Mentor wants a bigger piece of the pie. It hopes the new Crystal2 chip will do just that along with VirtuaLAB…

Satin to introduce automated design monitoring at DAC 2012

The folks at Satin Technologies have a painful problem (and it's not one you can make go away by rubbing cream on it).

Cadence forges closer links between verification components

For a long time, it has been said that verification gets no respect. Aspects of this continue to be true, but tool development keeps heading forward…

News & Analysis

EE Times Live Stream

EE Times Live Stream @ DAC 2012

EVE accelerates S/W development for TI's OMAP 5

FPGA-based H/W-assisted ZeBu-Server verification platform performed 30X faster than closest competitor

ASTC, Tanner EDA to deliver ASIC design services

Australian Semiconductor Technology Co. and Tanner EDA have reached an agreement to deliver analog/mixed signal IP and custom ASIC design services.

Cadence tools tape out 20-nm SoC test chip for ST

Cadence Design Systems has announced it has helped tape out STMicroelectronics' 20nm test SoC chip, an industry milestone for Cadence delivering an end-to-end mixed-signal design flow for 20 nm.

Snapped up before DAC – there will be no Missing Link

One of the new exhibitors for DAC this year has been snapped up before the show begins… .


Gearing Up for DAC – Verification demos

This entry is the first in the what to see at DAC blogs. It includes listing about the demos that companies will be showing in the area of verification…

Gearing Up for DAC – Above RTL

This is the second in the series of what to see at DAC blogs. It includes listing about the demos that companies will be showing in the area of design above RTL…

Gearing up for DAC – RTL to GDS II demos

This entry is the third in the what to see at DAC blog series. It includes listing about the demos that companies will be showing in the area of RTL to GDS II…

Gearing Up for DAC – IP, Flows and Services

This entry is the final entry in the what to see at DAC blog series. It includes listing about the demos

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