|
Tech Focus: Power – The real driver behind integrating HW/SW design?
HIGHLIGHTS
Using drowsy cores to lower power in multicore SoCs
Managing power in embedded applications using dual operating systems
Reduce SoC device/package leakage/power with improved power management protocols
Editor's Note
Many pressures are driving embedded systems developers to higher level tools to integrate hardware/software design, debug and verification: larger code sizes; more complex processors or SoC architectures; and the need for more reliability and security. But perhaps the most potent driver of all is the compelling need for lower power and more energy-efficient operation without sacrificing performance.
Solving this demanding and difficult equation often forces designers to search outside their particular areas of expertise for answers: software developers are learning much more about the processor architectures and the underlying chip-level logic design; semiconductor process engineers are becoming more aware of what the software/hardware application environment demands; and SoC processor architecture designers are dealing with both.
In their quest for solutions, embedded developers are also moving to high level tool environments that allow teams of engineers to move back and forth between several levels of the design. For example, in “ Using SystemC to build a system-on-chip platform , ” TI’s OMAP team describes the wide array of hardware and software tools they used to build, simulate, and test hardware and software that achieve high performance at low power. In “ Reduce SoC device/package leakage/power with improved power management protocols,” Freescale process engineers describe how an understanding of the packaging and pinout requirements of their SoC design allowed them to develop a chip-level protocol that significantly reduces power. In “ Managing power in embedded applications using dual operating systems , ” Loc Truong details how appropriate use of RTOS features such as interprocess communication and state machines can further reduce power demands beyond what developers have been able to achieve in hardware alone.
Of the articles selected for this issue of the newsletter, my Editors Top Picks about this delicate balancing act are:
Using drowsy cores to lower power in multicore SoCs
Choosing the right low power processor for your design
The why, where and what of low-power SoC design
What is power aware debugging?
What tools and techniques are you and your teammates using to coordinate this delicate dance between hardware and software design? Between high performance and low power? Which ones work and which do not? What tools do you need to satisfy these conflicting requirements? What has been your experience and what do you think other developers need to keep in mind?
Design How Tos
Using drowsy cores to lower power in multicore SoCs
Freescale engineers describe a cascading power management technique that steers tasks to a smaller number of cores during non-peak activity periods so that the idle cores can enter a minimal-power or “drowsy” state.
Managing power in embedded applications using dual operating systems
In this product how to article, TI's Loc Truong describes how to use inter-processor communication and state machine design to reduce the overall system power in a heterogeneous dual-core system.
Reduce SoC device/package leakage/power with improved power management protocols
Described is a new power domain partitioning technique to reduced leakage in system-on-chip designs by taking advantage of package configuration information.
Using SystemC to build a system-on-chip platform
How Texas Instruments' designers used the SystemC hardware design language to do performance modeling when creating both the company's OMAP-2 platform and the devices based on it.
Power aware verification of ARM-based designs
How to deal with the challenges of power aware verification in SoCs and use IEEE 1801-2009 Unified Power Format to define power management architecture for verifying a power-managed ARM-based design. (Paper from ARM TechCon 2010.)
Managing power consumption on your portable applications processor design
New circuits which combine low dropout regulator and buck converter functions can be used to reduce power in many portable application processor designs.
System level software centric power debugging using virtual prototypes
Achim Nohl of Synopsys describes how Virtual Prototypes (VPs) provide all the necessary elements for a debug solution that can spot and remove power related defects from software.
What is power debugging?
Power debugging is beginning to appear as a concept in the embedded industry, but what do we mean? In this article we will take a look at what is driving this need in embedded systems, and the way to optimize software to minimize an application’s power consumption.
Product How-To On: Exploring Multicore Power Management with Modeling and Simulation
How to use Mirabilis Design's VisualSim to model and provide accurate results and the task/power efficiency metrics for multicore designs running at different clock speeds with completely different power algorithms.
Things to keep in mind when designing power management circuitry
This article compares the performances of a switch mode power supply and a typical power inductor during high temperature conditions, and describes methods for measuring thermal resistance and thermal capacitance to ambient are discussed.
Choosing the right low power processor for your embedded design
Here are some suggestions about design criteria you need to consider when selecting a low power processor for your embedded system design needs
The why, where and what of low-power SoC design
Minimizing power consumption is a huge challenge for nanometer systems-on-chip. In this tutorial article, Cadence Design Systems' Pete Bennett (right) shows why that's the case, and details techniques that can help, including multiple voltage domains, clock phasing, and clock gating.
Embedded Systems Bookshelf
Excerpts
Embedded Books Reading Room
Bernard Cole's favorite links to book excerpts.
Reviews
Engineer's Bookshelf
Airport fiction blows. A look at books other engineers are reading and why you should read them, too. Recommend and write a review yourself. E-mail Brian Fuller.
Jack Ganssle's Bookshelf
A list of book reviews by Jack Ganssle, contributing technical editor of Embedded Systems Design and Embedded.com.
Max's Cool Beans
Clive “Max” Maxfield, the editor on Programmable Logic DesignLine, often writes about interesting books.
Products
IAR Sytems adds power debugging to Embedded Workbench
IAR Systems has added power debug and analysis tools as standard features of IAR Embedded Workbench for ARM.
Dialog adds ARM multicore support for next-generation system-level power management ICs
Dialog has launched two third-generation advanced system-level power management ICs for tablet PCs, smartphones, embedded computers and multimedia players.
Monolithic 3D offers IC power simulator
Monolithic 3D Inc., previously known as NuPGA, has released an open-source simulator for assessing power consumption and connectivity of single and 3-D components called IntSim v2.0.
Renesas targets ultra low power with RX200
The first member in a new ultra low power family of MCUs from Renesas extends the RX range in to portable appliances.
STM32L ultra-low-power ARM Cortex-M3 MCUs for Energy-Lite apps
STMicroelectronics has announced the extension of its 32-bit STM32L series of microcontrollers to include devices with memory densities of 256 and 384 Kbytes, offering a Flash memory range from 32 up to 384 Kbytes for embedded applications.
Energy Micro extends ultra-low-power Gecko MCU family with Cortex-M0 and enhances Tiny product performance
Energy Micro is extending its ultra low power EFM32 Gecko microcontroller (MCU) family with the introduction of an ARM Cortex-M0 based product line. The company has also improved the low power performance of its forthcoming Cortex-M3 based Tiny Gecko devices. The new introductions will boost the company's Energy Friendly Microcontroller portfolio to more than 100 products.
|
