Embedded.com Tech Focus Newsletter (8-22-11): MCUs/MPUs & FPGAs–Erasing the boundaries

Embedded Newsletter for 8/22/11

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August 22, 2011

Tech Focus: MCUs/MPUs & FPGAs – Erasing the boundaries


Developing processor-compatible C-code for FPGA hardware acceleration

Basics of core-based FPGA design: Part 1 – core types & trade-offs

Designing with core-based high-density FPGAs

Editor's Note

Bernard Cole Bernard Cole
Site Editor

With the availability of platform FPGAs built around standard processor architectures and emergence of high level design tools such as SystemC, Handel-C and new advanced C-to-FPGA compilers , the line separating development on microcontrollers and on FPGAs is rapidly disappearing.

In “Designing with core-based FPGAs“, Robert S. Grimes points out that it is now possible for a single developer build a sophisticated multicore embedded FPGA design that meets the demands of even high reliability military/aerospace systems. But he emphasizes that the key elements are not only the right set of tools and building blocks, but using them in ways that optimize your design, not hinder it.

Two other articles I recommend as Editor's Top Picks are “Basics of core-based FPGA design“, a four part series on platform FPGA design, and “Developing processor-compatible C-code for FPGAs “, by David Pellerin and Brian Durwood.

You can learn more about these topics by registering for the Fall 2011 ESC in Boston and attending one of several courses on advanced embedded FPGA design, including:

FPGA design for embedded systems (ESC-102)
FPGA partial reconfiguration in multicore design (ESC-202)
FPGA-based prototyping (ESC-405)
Model-based design for FPGA development (ESC-212)
Multicore & real time: making it work with FPGAs (ESC-404)

And of course I've included in this newsletter the usual round-up of recent articles, white papers, and webinars on these topics, as well a roundup of recent stories on the upcoming Embebedded Systems Conference.

Design How-Tos

Developing processor-compatible C-code for FPGA hardware acceleration

This article describes an iterative process for converting C code to run on FPGAs with or without processor cores, how to identify which code sections can best benefit from hardware acceleration, and coding styles to use to retain commonality.

Designing with core-based high-density FPGAs

One engineer's adventures designing with microprocessor-based FPGAs.

Basics of core-based FPGA design: Part 1 – core types & trade-offs

In Part 1 in this four part series, the authors of “Rapid System Prototyping with FPGAs,” provide an overview of FPGA processor core types – firm, hard and soft – and the pros and cons that need to be evaluated in the context of an embedded system's requirements.

Basics of core-based FPGA design: Part 2 – System design considerations

In Part 2 in this four part series, the authors of “Rapid System Prototyping with FPGAs,” do a detailed analysis system design issues to be considered: use of codesign, architectural implementation, processor & peripheral selection as well as software implementation issues.

Basics of core-based FPGA design: Part 3 – Picking the right core options

In Part 3 in this four part series, the authors of “Rapid System Prototyping with FPGAs,” discuss various implementation issues including peripheral functions and RTOS selection.

Basics of core-based FPGA design: Part 4 – Implementing a design

In Part 4 in a series, after laying down the basics of core-based development with FPGAs, the authors of “Rapid System Prototyping with FPGAs,” take the reader through the process of an example design.

Accelerate system performance with hybrid multiprocessing and FPGAs

Multiprocessing is becoming a key differentiator for FPGA-based processor architectures.

Product How-To: Building a configurable embedded processor – From Impulse C to FPGA

By combining Xilinx FPGAs and Impulse's EDA tools with a bit of ingenuity, embedded designers can extend the instruction set of the processors running in the FPGAs to add their own functions to a design.

Reducing Power in Embedded Systems by Adding Hardware Accelerators

In addition to creating accelerator hardware designs for key algorithm steps, developers should consider using multiple copies of such accelerators and run them in parallel and optimize for both power and performance.

Designing with an embedded soft-core processor

Engineers from Plexus Technology provide some insight into designing a soft-core processor embedded in an FPGA and highlight key factors to consider in designing a System on a Programmable Chip (SoPC).

The art of FPGA construction

Working with FPGAs isn't intimidating when you know the basic techniques and options.

Compiling software to gates

Are VHDL and Verilog past their prime, soon to be replaced by C-like design languages such as System C, Handel-C, and others? Professor Ian Page thinks a change is at hand.

Hardware Design Requires Hardware Design Languages

While languages such as C++ can help in the creation of high-level models of hardware, Sean Dart argues that hardware engineers need specific language constructs in languages such as SystemC that allow them to express their intent in the most accurate and productive manner.

Generate FPGA accelerators from C

A simple FFT, generated as hardware from C language, illustrates how quickly a software concept can be taken to hardware and how little you need to know about FPGAs to use them for application acceleration.

Handel-C backs top-down hardware development

Hardware-based methodologies used in ASICs and FPGAs have evolved from a bottom-up approach in which hardware functionality is developed by describing circuit structure. To this end, such approaches have focused on maintaining low-level design control.

FPGA Soft Processor Design Considerations

FPGA technology and soft processor cores have the potential to integrate system design into a single FPGA device. From definitions to implementation, what do you need to know to get there?

Embedded Systems Bookshelf


Embedded Books Reading Room
Bernard Cole's favorite links to book excerpts.


Engineer's Bookshelf
Airport fiction blows. A look at books other engineers are reading and why you should read them, too. Recommend and write a review yourself. E-mail Brian Fuller.

Jack Ganssle's Bookshelf
A list of book reviews by Jack Ganssle, contributing technical editor of Embedded Systems Design and Embedded.com.

Max's Cool Beans
Clive “Max” Maxfield, the editor on Programmable Logic DesignLine, often writes about interesting books.


Virtex-6 in volume production on UMC's 40-nm process

Xilinx announced that it has fully qualified the Virtex-6 FPGA family on UMC's 40-nm logic process.

Altera, MIPS roll FPGA-optimized soft processor

Altera, MIPS Technologies and System Level Solutions introduced a MIPS-based FPGA optimized soft processor for use on Altera's FPGAs and ASICs to create solutions for networking, video and digital signal processing applications.

Altera's Quartus II design software features Qsys System Integration Tool

The industry's first FPGA-Optimized Network-on-a-Chip (NoC) interconnect delivers up to 2X the performance versus SOPC Builder.

Actel rolls library of IP cores for SmartFusion

Actel announced the availability of a broad portfolio of Actel IP cores available for its SmartFusion mixed-signal FPGAs.

PSoC Designer 5.0 combines code-free design with customization capabilities

Cypress Semiconductor has introduced PSoC Designer 5.0, which the company touts as the industry's first and only integrated design environment that includes both code-free and high-level language programming modes in one package.

News & Analysis

ESC Boston becomes rich tech carnival next month

The upcoming Embedded Systems Conference Boston has expanded into an umbrella venue for embedded system developers, hardware designers and engineers who just like to peek at what's “under the hood.”

Xilinx provides details on ARM-based devices


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