|TI'S OMAP4/ NEC'S QUAD CORTEX-A9/ TI MULTICORE DSP/ DESIGN BY CONTRACT|
|If you thought the technology pace might slow down a bit now thatISSCC 2010 is over, forget it. This week at the Mobile World Congress, NEC showed its quad-core Cortex-A9 SoCand TI's sampling itsnextgen 45-nm OMAP4 SoC. In addition, TI has launched an SoC architecture basedon its multicore DSPs . And at a meeting at U.C. Berkeley'sParallel Computing Lab, multicore researchers expressed guarded optimism aboutprogress in parallel programming.
With all this focus on serious multicore system-on-chip designs bythe big companies such as TI, NEC, Intell and ARM, the rest of usbetter break out the books and get up to speed. To get you started I'vegathered some relevant design articles that ran on-line this week: managing complex SoCdesign with plan-based verification, metric-driven complex SoC design, a newapproach RTL implementation, partitioningASICs , functional verification methodologiesand virtualizedsystem development .
In addition to a new column from Jack Ganssle on “Executing softwarecontracts ,” you might also find it enlightening to read a Product How-To on TI's controlSUITEtools for it's C2000 Piccolo MCUs , anintegrated bias approach to LCD segment drive pin assignmentand using smart drivers to reduce energy usein embedded consumer devices. Good reading!! (Embedded.com Editor Bernard Cole,email@example.com )
|TOP INDUSTRY NEWS|
|TI launches multicore SoC architecture
Texas Instruments Inc. (Dallas, Texas) has launched a system-on-chip architecture based on its multicore DSPs.
|Split architecture for handsets to continue, says TI exec
The so-called “split architecture” for mobile phones is going to continue and prosper according to Greg Delagi, senior vice president and general manager of Texas Instruments' Wireless Terminals business unit.
|TI samples OMAP 4, but only to big players
Texas Instruments is sampling its Omap-4 application processor implemented on a 45-nm manufacturing process technology, the company said at the Mobile World Congress. But added the caveat that OMAP 4 is only intended for high-volume OEMs and ODMs and the part will not be sold through distributors.
|NEC to show quad-core Cortex-A9 processor
NEC Electronics Corp. looks set to grab the lead in terms of high performance ARM processors at the Mobile World Congress in Barcelona next week with a quad-core Cortex-A9 design. The technology is due to showcased on the booth of ARM Holdings plc (Cambridge, England), the originator of the Cortex-A9 multiprocessing core.
|Berkeley discusses progress in parallel programming
Researchers from the University of California at Berkeley gave an update on their work to find new programming models for tomorrow's many-core processors and announced two new research centers—one focused on low-power circuits and another on cloud computing.
|BREAK POINT by Jack Ganssle|
|Executing software contracts
A new tool writes DBC-like contracts for you
|The evolution of the general-purpose oscilloscope
The move from analog to digital was just the first step in a long line of enhancements.
|EDITOR'S TOP PICK by Bernard Cole, Embedded.com Editor|
|Reducing Costs, Risks, Time to Market with Virtualized Systems Development
To achieve developer efficiency and software quality with virtual system development tools, it is necessary to use a fully-featured simulation infrastructure with the ability to create custom models.
|DESIGN FOCUS: SoC/ASIC Development|
|Managing Complex SoC verification using plan based verification techniques
Meeting the quality requirements of a complex SoC requires managing large verification projects. In this article, Freescale and STMicroelectronics recount a recent experience with a verification management solution (Incisive Enterprise Manager) from Cadence, for the verification of a 32-bit microcontroller project for the automotive industry.
|Guidelines for complex SoC verification
As verification takes up a significant part of the design cycle, planning, managing the project dynamics and a metrics-driven execution will be of much help says the author, a senior ASIC engineer
|Verifying the border line between auto hardware, software
Many problems occur when hardware meets software, especially in auto applications. This is where functional verification methodologies from the hardware world can be very useful.
|A new approach to RTL implementation
Chip synthesis is a new approach to turning register transfer level (RTL) code into gates a whole chip at a time.
|Partitioning an ASIC design into multiple FPGAs
This article outlines the most common approaches and flows to consider before you embark on your next partitioning project. Ultimately, you can accelerate the verification phase by using an ASIC prototyping approach that allows you to build multi-FPGA based prototypes of ASIC designs in an intuitive fashion, with little or no modifications to the original design.
|PRODUCT HOW-TO ARTICLES|
|Adapting MCU software to meet your design needs
How C2000 MCU developers can use TI's Eclipse IDE-based controlSUITE tool framework to accelerate development of applications for a wide range of microcontroller-based consumer devices.
|An integrated bias approach to LCD segment drive pin assignment
The ability to assign any pin as a segment or common output simplifies PCB layout and maximizes use of onboard peripherals, as well as reduce time needed to develop segment LCD drive firmware.
|Using smart drivers to reduce energy use , PCB clutter in portable apps
Small portable electronic systems such as mobile telephones, personal media players (PMPs), digital still cameras (DSCs), digital video cameras (DVCs), portable medical equipment (PME), and global-positioning systems (GPS) continue to evolve and add features with each generation. As they do, their peripheral-circuit requirements have become more similar in part because their power sources, ports, and MMIs (man-machine interfaces) draw on similar technologies.
|Looking ahead: Data converter trends for 2010
Converters are key to mixed-signal products; here's a perspective on where they are headed in terms of performance, power, and functionality. . . .
|EDITOR'S NOTE by Bernard Cole, Embedded.com Editor|
|If you want to learn how to deal with the inevitable signal-integrity problems in your design, check out the TechOnLine course: Fundamentals of Signal Integrity. It will take you from a basic definition of signal integrity and what can cause it to deteriorate, right through to the interpretation of an eye diagram and how use the latest test equipment to spot problems.
Also, to learn more about multicore design using Linux check out the new Live Webinar: “Optimized Linux Development Tools for Multicore”. Presented by Alex deVries, Chief Linux Technologist, and Emeka Nwafor, Director of Product Management, Development Tools, both from Wind River Systems, it covers the basics of how to use Wind River's Eclipse based visualization enhancements to Linux command line tools to migrate existing code or developing new code for a multicore processor.