Editor’s Note: As advanced algorithms continue to emerge for smart product designs, developers often find themselves struggling to implement embedded systems able to meet the associated processing demands of these algorithms. FPGAs can deliver the required performance, but designing with FPGAs has long been considered limited to the purview of FPGA programming experts. Today, however, the availability of more powerful FPGAs and more effective development environments has made FPGA development broadly accessible. In this excerpt, Chapter 4 from the book Architecting High-Performance Embedded Systems, the author offers a comprehensive review of FPGA devices, implementation languages, and the FPGA development process as well as a detailed walkthrough of how to get started implementing FPGAs in your own design. The complete excerpt is presented in the following series of installments:
1: Hardware resources
2: Implementation languages
3: Development process
4: Building a project (this article)
Adapted from Architecting High-Performance Embedded Systems, by Jim Ledin.
Developing your first FPGA project
In this section, we will develop and implement a simple but complete project using a Xilinx Artix-7 FPGA device installed on a Digilent Arty A7 development board. This board comes in two variants, a lower-cost version (US $129) with a model number ending in-35T and a more capable, but more costly, version (US $249) with a model number ending in -100T. The only difference between the two boards is the model of the Artix-7 FPGA installed on the board. As you would expect, the -35T has fewer resources available than the -100T.
You can use either the -35T or the -100T variant for this project. The only difference in the development process is specifying the correct board model whenever the need arises. However, in later chapters, the -100T variant will be required due to the resource requirements of the example digital oscilloscope project design, so the more capable board is recommended.
The Arty A7 boards are available for purchase at https://store.digilentinc.com/arty-a7-artix-7-fpga-development-board-for-makers-and-hobbyists/ and from other sources, such as Amazon.
For the purpose of this project, the resources on the board of interest are the FPGA device itself, as well as the four switches, four pushbuttons, and five LEDs. This project will demonstrate how to install the Vivado tool suite, create a project, enter HDL code, test the code, and ultimately produce a bitstream and download it to the board. After downloading the bitstream to the board, you will be able to manually test the operation of the system. You will also see how to program the FPGA image into flash memory on the Arty A7 board so that it loads and runs each time the board powers on.
This project will implement a four-bit binary adder in the FPGA. This is intentionally a very simple design because the focus here is on setting up the tools and learning how to use them, and not on implementing a complex HDL model.
The four switches on the board represent one 4-bit binary number and the four pushbuttons represent another 4-bit number. The FPGA logic will continuously perform an addition operation between these two numbers and display the result as a 4-bit binary number on four LEDs with a fifth LED representing the carry bit.
The 4-bit adder code is based on the single-bit full adder circuit described in the Hardware design languages section of Chapter 1, Architecting High-Performance Embedded Systems.
Installing the Vivado tools
We will use the Xilinx Vivado suite of FPGA development tools for this project and for projects in future chapters. These tools are available for free and are supported on Windows and Linux operating systems. You may install the tools on either operating system. The description in this section covers the Windows version of the tools, but if you are installing on Linux, the differences should be obvious. Working with the Vivado tools should be nearly identical on the different operating systems:
- If you don’t already have one, create a Xilinx user account at https://www.xilinx.com/registration/create-account.html.
- Visit https://xilinx.com and log in to your user account. Once logged in, go to the tools download page at https://www.xilinx.com/support/download.html.
- Download the Xilinx Unified Installer: Windows Self-Extracting Web Installer. You should probably select the latest version available, but if you want to follow along with the version used in this book, select version 2020.1.
- The installer file will have a name similar to Xilinx_ 1_0602_1208_Win64.exe. Locate this file in your downloads directory and run it. If a dialog warns you about installing an app that isn’t Microsoft-verified, click Install anyway.
- When the Welcome screen comes up, click Next:
Figure 4.3 – Installer Welcome dialog
- On the following screen, enter your xilinx.com user ID and password, then click Next:
Figure 4.4 – Installer login dialog
- The next dialog requests that you accept some license agreements. Check the boxes that say I Agree, then click Next.
- In the next dialog, leave Vitis selected as the product to be installed and click Next. Vitis includes the Vivado tool suite along with a collection of other Xilinx development tools:
Figure 4.5 – Installer product selection dialog
- The next dialog allows you to select the software components to be installed. Leave the selections at their default values and click Next.
- The next dialog allows you to select a destination directory and specify program shortcut options. A destination directory of C:\Xilinx is a suitable location. Create this directory if it does not exist. Click Next.
- The next dialog displays a summary of the installation options. Click Install to proceed with the installation. Depending on the speed of your computer and your internet connection, installation may take a few hours to complete:
Figure 4.6 – Installation complete dialog
Having completed the installation, we will next create our first project.
Creating a project
Follow these steps to create and build the 4-bit binary adder project for the Arty A7 board:
- Locate the desktop icon titled Vivado 2020.1 (or look for your version number, if different) and double-click it.
- When Vivado displays its main screen, click Create Project in the Quick Start section:
Figure 4.7 – Vivado Quick Start dialog
- This will start the Create a New Vivado Project wizard. Click Next to reach the Project Name page and enter ArtyAdder as the project name. Select an appropriate directory location for the project and check the box to create a subdirectory, then click Next. Examples in this book will use the C:\Projects directory as the location for all projects:
Figure 4.8 – Project Name dialog
- In the Project Type dialog, select RTL Project and check the box next to Do not specify sources at this time. Click Next:
Figure 4.9 – Project Type dialog
- In the Default Part dialog, click the Boards tab and type Arty into the Search field. Depending on the board type you have (or if you don’t have a board yet), select either the Arty A7-100 or Arty A7-35 and click Next:
Figure 4.10 – Default Part dialog
- In the New Project Summary dialog, click Finish.
We have now created an empty project. In the next section, we will create VHDL source files containing the logic circuit design for this project.
Creating VHDL source files
The following steps describe the process of creating VHDL source files, entering source code, and compiling the FPGA design:
- In the Sources sub-window, right-click Design Sources and select Add Sources…:
Figure 4.11 – Add Sources… menu selection
- In the Add Sources dialog, ensure Add or create design sources is selected, then click Next.
- In the Add or Create Design Sources dialog, click Create File:
Figure 4.12 – Add or Create Design Sources dialog
- Enter the filename FullAdder.vhdl and click OK:
Figure 4.13 – Create Source File dialog
- Repeat the previous two steps to create another file named Adder4.vhdl, then click Finish in the Add or Create Design Sources dialog.
- The Define Modules dialog will appear next. We will not be entering anything here. Click OK to close this You will be asked if you are sure you want to use these values. Click Yes:
Figure 4.14 – Define Modules dialog
- Expand the Non-module Files under Design Sources, then double-click FullAdder.vhdl. An editor window will open displaying the empty FullAdder.vhdl file:
Figure 4.15 – Newly created source file
- Enter the following VHDL code into the FullAdder.vhdl editor window:
-- Load the standard libraries library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Define the full adder inputs and outputs entity FULL_ADDER is port ( A : in std_logic; B : in std_logic; C_IN : in std_logic; S : out std_logic; C_OUT : out std_logic ); end entity FULL_ADDER; -- Define the behavior of the full adder architecture BEHAVIORAL of FULL_ADDER is begin S <= (A XOR B) XOR C_IN; C_OUT <= (A AND B) OR ((A XOR B) AND C_IN); end architecture BEHAVIORAL;
This is the same single-bit full adder code we examined in the Hardware design languages section of Chapter 1, Architecting High-Performance Embedded Systems. Figure 4.16 shows the code in the Vivado editor window:
Figure 4.16 – FullAdder.vhdl source code
- In the same manner, double-click Adder4(Behavioral) (Adder4.vhdl) under Design Sources. Delete the automatically populated contents of the Adder4.vhdl editor window and enter the following code into the Adder4.vhdl editor:
-- Load the standard libraries library IEEE; use IEEE.STD_LOGIC_1164.ALL; -- Define the 4-bit adder inputs and outputs entity ADDER4 is port ( A4 : in std_logic_vector(3 downto 0); B4 : in std_logic_vector(3 downto 0); SUM4 : out std_logic_vector(3 downto 0); C_OUT4 : out std_logic ); end entity ADDER4; -- Define the behavior of the 4-bit adder architecture BEHAVIORAL of ADDER4 is -- Reference the previous definition of the full adder component FULL_ADDER is port ( A : in std_logic; B : in std_logic; C_IN : in std_logic; S : out std_logic; C_OUT : out std_logic ); end component; -- Define the signals used internally in the 4-bit adder signal c0, c1, c2 : std_logic; begin -- The carry input to the first adder is set to 0 FULL_ADDER0 : FULL_ADDER port map ( A => A4(0), B => B4(0), C_IN => '0', S => SUM4(0), C_OUT => c0 ); FULL_ADDER1 : FULL_ADDER port map ( A => A4(1), B => B4(1), C_IN => c0, S => SUM4(1), C_OUT => c1 ); FULL_ADDER2 : FULL_ADDER port map ( A => A4(2), B => B4(2), C_IN => c1, S => SUM4(2), C_OUT => c2 ); FULL_ADDER3 : FULL_ADDER port map ( A => A4(3), B => B4(3), C_IN => c2, S => SUM4(3), C_OUT => C_OUT4 ); end architecture BEHAVIORAL;
This code instantiates four copies of the single-bit full adder. The carry into the least significant adder is set to zero and the carry from each adder ripples to the next most-significant adder. The result of adding two 4-bit numbers is a 4-bit result and a single-bit carry:
Figure 4.17 – Adder4.vhdl source code
The next article will show how to test the design and implement our design for the Arty board.
Reprinted with permission from Packt Publishing. Copyright © 2021 Packt Publishing
|Jim Ledin is the CEO of Ledin Engineering, Inc. Jim is an expert in embedded software and hardware design, development, and testing. He is also accomplished in embedded system cybersecurity assessment and penetration testing. He has a B.S. degree in aerospace engineering from Iowa State University and an M.S. degree in electrical and computer engineering from Georgia Institute of Technology. Jim is a registered professional electrical engineer in California, a Certified Information System Security Professional (CISSP), a Certified Ethical Hacker (CEH), and a Certified Penetration Tester (CPT).|
- Embedded design with FPGAs: Hardware resources
- Embedded design with FPGAs: Implementation languages
- Embedded design with FPGAs: Development process
- Open-source tools help simplify FPGA programming
- Implementing floating-point algorithms in FPGAs or ASICs
- Leveraging FPGAs for deep learning
- Software tools migrate GPU code to FPGAs for AI applications
- FPGAs displace ASICs in Subaru Eyesight vision-based ADAS
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