Embedded system timing analysis basics: Part 1 - Timing is essential - Embedded.com

Embedded system timing analysis basics: Part 1 – Timing is essential

Just as in comedy, timing is essential to the success of a microcomputer design. Often it is quite possible to get one system functioning by simply interconnecting the various compo­nents. But it is significantly more difficult to be able to guarantee that many systems will work under the entire range of possible conditions that they may be exposed to.

There are many designs in production right now that have a number of unidentified failures due to the lack of a worst-case analysis of the design. When timing or loading problems show up in a design, they usually appear as intermittent failures or as sensitivity to power supply fluctuations, tempera­ture changes, and so on.

A worst-case design takes into account all available information regarding the components to be used with respect to variations in performance. Even when all parameters are at their most adverse values, the worst-case design can still be proved to meet the specifications.

These variants may be due to changing manufacturing conditions, temperature, voltage, and other variables. Without performing a detailed analysis, there is no way of knowing if the design will work reliably under all operating conditions. It is much better to design reliability and simplicity of manufacturing into a product using worst-case design rules than to attempt to correct a problem after the design has been implemented.

With the emphasis that must be given to the quality of the final product, a designer is obligated to perform a detailed examination of the timing in a system. As is the case in most quality improvements, these efforts result in direct cost and saving time. This is clearly one of the places where the designer can have the greatest impact on overall product quality.

Timing Diagram Notation Conventions

Timing notation is illustrated in Figure 6.1 below . The timing notation used in manufacturers’ data sheets may vary from this notation but is usually very similar. It is also important to notice that although the diagrams are reasonably standard, there is a wide variation in the selection of symbols for each timing parameter.

 

Figure 6.1: Timing diagram notation as used in this article.

The purpose of timing analysis is to determine the sequence of events in each of the bus cycles so that we can delimit, among other things, the time available for each of the components to respond to changes. This time is compared to the requirements as specified in the manufacturers’ data sheets to determine whether they are compatible and by what margin.

The most important timing specifications for interfacing components to a bus-oriented design are:

• Rise/fall time

• Propagation delay time

• Setup time

• Hold time

• Tri-state enable and disable delays

• Pulse width

• Clock frequency

There are two general classes of logic: combinatorial and sequential. Combinatorial logic has no memory and its output is some logical function of its current inputs, after some delay. Examples of combinatorial logic include gates, buffers, inverters, multiplexers, and decoders. Sequential logic has memory, which means that its outputs are a function of both current and past inputs.

Examples of sequential logic are flip-flops, registers, microprocessors, and counters. There are two types of sequential logic. Synchronous logic is synchronized to change only when there is a clock transition. In contrast, asynchronous logic does not use a clock signal.

Almost all the logic used in a microcomputer design will either be unclocked asynchronous logic (gates, decoders) or clocked synchronous logic (counter, latch or microprocessor). Some types of devices are available in either form. Each of the timing specifications in the following discussion is described using simple logic devices as they are typically used in embedded computer designs.

Rise and Fall Times

The rise time of a signal is usually defined as the time required for a logic signal voltage to change from 20% to 80% of its final value. The fall time is from 80% to 20%, as shown in Figure 6.2 below . These times are also commonly defined by some manufacturers as the transitions between the 10% and 90% levels.

 

Figure 6.2. Rise and fall times of a signal

Propagation Delays. The propagation delay is the time it takes for a change at the input of a device to cause a change at the output. All devices—even wires—exhibit some propagation delay. Some devices do not have symmetrical delays for positive and negative transitions. In Figure 6.3 below , the propa­gation times for a high to low transition are shorter than for a low to high transition.

 

Figure 6.3. Propagation delay

This asymmetrical delay is common for TTL and open collector and open drain outputs because they are better at sinking current than sourcing it. Thus, the load capacitance is charged more slowly when the current is being supplied from the weaker “high side” or pull-up device. Propagation delays are usually measured from the 50% amplitude points, as shown in Figure 6.3.

Setup and Hold Time

In Figure 6.4 below , a standard D type flip-flop (e.g., a 74xx74 device) is shown along with a sample timing diagram that illustrates the operation and key timing parameters of a flip-flop. This type of flip-flop samples the D input whenever the clock (CK) line goes high, and after a delay, the output remains in the same state until the next rising edge on the clock line.

The triangle on the clock input indicates that it is a rising edge sensitive input, meaning that it will only have an effect when there is a rising edge on the clock pin. A falling edge sensitive input would have a bubble outside the block where the clock enters the flip-flop. In order to be able to guarantee that the flip-flop will operate correctly, the D input must be stable during the setup and hold time. 

Figure 6.4: Setup and hold time.

Figure 6.4 also shows the propagation delay from clock to Q out (TPCKQ), the setup time (TSU), and the hold time (TH). Setup time is the amount of time a sampled input signal must be valid and stable prior to a clock signal transition. Hold time is the amount of time that a sampled signal must be held valid and stable after a clock signal transition occurs.

If these conditions are not met, the Q output may become invalid or even oscillate. This condition is referred to as metastability. The times of these and most other signals are frequently measured with respect to the 50% amplitude points of the clock signal rather than the valid logic one and zero levels. An analogy for the flip-flop as a sampling device is that of an instant camera:

The clock is the shutter, the D input is the lens, and the output is the film image. The input is sampled when the shutter is open, and if the subject moves with the shutter open, the picture will be blurred. For the fl ip-flop, the “shutter open” time, referred to as the window of uncertainty, is shown in Figure 6.5 below , along with some possible results.


Figure 6.5: Metastability of a flip-flop.

Metastability of a storage device such as a flip-flop or register is caused by the change of an input signal too close to the edge of the clock signal. In other words, if the setup or hold time requirements are not met, the output of the device is unpredictable and may even be unstable. The output may operate normally, take an invalid level, or oscillate (which could also explain why indecisive people take bad photos!).

Tri-State Bus Interfacing

When multiple devices are capable of driving the same line, the possibility exists that two or more of them will try to drive it in opposite directions at the same time. When tri-state devices fight like this it is called bus contention. Figure 6.6 below illustrates this condition. Although the data is unpredictable during this period, there are far worse things that can happen as a result of this condition.

Since most tri-state devices have the ability to drive many loads, they are also capable of sourcing and sinking large currents. When two of these devices are in contention, very large currents with peaks in the tens or hundreds of amperes can flow for time periods on the order of nanoseconds.

 

Figure 6.6: Tri-state bus timing and contention.

The large current spikes that occur during contention may stress the devices and significantlyreduce their reliability. A far more frequent problem, however, is the temporary drop or glitch in the local power supply wires that can cause any other nearby devices to change state. As you can imagine, this can create havoc in sequential logic, particularly for micros.

Based on past experience with Murphy’s Law, these glitches generally seem to change the current instruction to “jump immediate to format hard disk routine,” thereby erasing all your data. In a properly designed system, there is a “dead time” when no device is driving the bus to act as a safety margin between the times that two devices are enabled to drive their outputs. The problems arise when the output enable time of a device which is just turning on is less than the output disable time of a device which is turning off.

Pulse Width and Clock Frequency

The width of a positive going pulse is the period beginning from its positive transition (rising edge or leading edge) to its negative transition (falling or trailing edge). Figure 6.7 below illustrates these concepts.

Figure 6.7: Pulse width, period, and clock frequency

Pulse widths are important in defining the operation of control signals such as the memory read or write signals and clocks. Clock signals used for modern microproces­sors usually, but do not always, have equal high and low pulse width requirements.

The period (T ) of a signal is the sum of the rise time, high time, fall time, and low time. The frequency of a processor clock ( f1/T ) may have a lower limit as well as an upper limit.

The stand­ard NMOS 8051 family of parts has a lower frequency limit of 1.2 MHz. That means that the processor cannot be operated at a lower frequency. The reason is that the processor’s internal design requires a constant clock to correctly maintain its state.

Other processors (such as the 80C51 series CMOS devices) can tolerate having their clock stopped completely, since they have been designed to maintain their internal states indefinitely, as long as power is applied.

Next in Part 2: Fan-out and loading analysis: DC and AC.

Ken Arnold, the author of Embedded Controller Hardware Design , is Embedded Computer Engineering Program Coordinator and an instructor at UCSD Extension, as well as founding director of the On-Line University of California. Ken was also the founder and CEO of HiTech Equipment Corp., CTO of Wireless Innovation and engineering chief at General Dynamics.

This article  is based on material from “Embedded Hardware know it all,”  used with permission from Newnes, a division of Elsevier. Copyright 2008. For more information about this title and other similar books, please visit www.elsevierdirect.com.

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