Embedded system timing analysis basics: Part 2 -Fan-out & loading analysis - Embedded.com

Embedded system timing analysis basics: Part 2 -Fan-out & loading analysis


Another important part of worst-case design is a realistic model of the signal loading for each of the circuit’s outputs. If insufficient drive is available, buffer circuits must be added or the number of loads must be reduced to guarantee correct operation. Fan-out is the number of equivalent inputs that can be safely driven by one output. A fan-out of 10 indicates that one device output can drive 10 inputs. The fan-out is determined from:

The source, type, and number of loads

• DC characteristics sources and load

• AC characteristics of the loads vs. the source test conditions

DC characteristics of the output and inputs consist of:

• The maximum current that can be produced by an output

• Maximum currents required to drive an input

The maximum output currents are specifiedas:

• IOLmin. Minimum output low (sink) current for a valid zero output voltage.

• IOHmin. Minimum output high (source) current for a valid one output voltage.

Note that a low output is sinking currents that are coming out of the inputs that are being driven. Likewise, a high output is sourcing current that goes into the inputs that are being driven.

Maximum currents required to drive an input are specified as:

• IILmax. Maximum input low current for a valid zero input voltage.

• IIHmax. Maximum input high current for a valid one input voltage.

Figure 6.8: Current sign for logic high.

Another important convention has to do with the sign of the current flowing in or out of a device pin. In most cases, current flowing into a device pin is given a positive sign (as shown in Figure 6.8 above ), whereas current flowing out of a pin is given a negative sign (as shown in Figure 6.9 below ).

In both Figures 6.8 and 6.9, the device on the left is the driving device, which tries to force its output to the desired logic state. In the logic one state, the output sources current (50 microampere), and the receiving device absorbs that current (50 microampere). In our example, the available output current is exactly equal to the input current used by the load, resulting in a DC fan-out of 1.

Figure 6.9: Current sign for logic low.

Unfortunately, this convention is not always followed consistently, so it is up to you to recog­nize the current direction from the context of the situation in which it appears. Generally, the current direction can be determined by keeping these images in mind, especially since many data sheets do not specify the sign for the input and output currents.

The other type of fan-out limitation is the ability of an output to drive the capacitance of the loads and stray wiring capacitance, also known as AC fan-out. The AC fan-out is determined by the specified test load for the driving chip and the load presented by the actual load capacitance.

The capacitive load is the parallel combination of all the input capacitances of the gate inputs attached to the signal, plus the wiring capacitance. Since the capacitors in parallel are equivalent to a single capacitor equal to the sum of the individual capacitances, we simply add up all the load capacitor values and compare this to the output’s specified test load.

The driving device’s specified load capacitance, CL, is the test load capacitance used by the manufacturer for specifying the AC or timing characteristics of the device. Most often, this specifi cation is listed in the test conditions or notes for the timing specifications of the chip.

As long as the sum of the load capacitances, including the stray wiring capacitance, is less than the specifiedtest load for the driving device, all the timing specifications will be valid as specified in the timing section of the data sheet.

If the driving device is overloaded (actual CL is greater than specifiedCL), then the timing specifications of the device need to be de-rated (slowed down), since additional capacitance will increase the rise and fall times of the signal line in question. Methods for estimating the amount that an overloaded output can withstand are described later.

AC characteristics of the outputs and the inputs consist of:

• CL . The load capacitance that an output is specified to drive is listed in the timing specifications for the driving device under the name “test conditions,” which is usually in the notes at the bottom of the specifi cation sheet.

• Cin . Maximum input capacitance of a driven input load.

• Cstray . Wiring and stray capacitance can be approximated to be in the range of 1 to 2 picofarads per inch of wiring on a typical PC board.

As long as the inequality below is satisfied, the signal will meet the timing specifi cations for the driving device. If the actual load is greater, it will delay:

Driving device spec CL > actual Cload = Cin1 Cin2 …Cwiring

The AC fan-out is limited by the parallel combination of the logic inputs’ capacitance, Cin, and the stray or wiring capacitance. Capacitors in parallel are additive, so the load presented to an output is the sum of the input capacitances of the logic inputs plus the wiring capacitance.

Logic input capacitance is often difficult to find, since it might not be listed in the component data sheet but rather in another section of the data book describing the characteristics common to all members of a given logic family.

Typical logic input capacitance ranges from 1 to 5 pF (picofarads or 1012F) but may be outside this range. The maximum load capacitance that a device is specified to drive (CL) is usually defined in the test conditions for the timing specifications of an integrated circuit, because it is the timing which is most affected by capacitance.

Load capacitance is usually specified in the range of 50 to 150 pF. Wiring capacitance is often in the range of 1 to 2 pF per inch of wire for a nominal printed circuit trace. Actual values can vary quite a bit, depending on the physical dimensions of the trace, proximity to surrounding signals, and distance from a ground plane, as well as the dielectric constant of the circuit board material.

Calculating Wiring Capacitance

The standard formula for determining capacitance is:

C = (ε* A)/d

where A is the area of two closely spaced parallel plates, d is the distance between the plates, and ε represents the permittivity of the material. (Permittivity is the measure of how easily a material can carry electric lines of force.)

For the purposes of this section, we can define the area, A, as the trace length multiplied by the trace width. Wiring capacitance is determined as a capacitance per unit length for a given trace width and distance from the ground or power plane.

Let’s examine a typical situation. For an eight-layer PC board with 8 mil traces and innermost layer ground/power planes, what is the capacitance per inch of trace on each of the signal layers?

Here are the terms we’ll use in the equations to solve this problem and their values:

• Trace width (w)8 mils (one mil equals 103 inch)

• Trace length (l)1000 mils

• Area (A)w times 1

• Total board thickness (T)0.062 inch

• Number of layers (N)8

• Number of layers separating power and ground plane (n)1

• Fringe effect and inter-trace stray capacitance adjustment factor ( f )1.7

• Permittivity of air (e)8.859 * 1012 * (coul2/(newton*m2))

• Relative permittivity of glass-epoxy dielectric (er) used in this example6

We start by determining the thickness of each dielectric layer, represented by t:

t = T/(N – 1)8.857 mils

Next we need to determine the distance between the trace and ground/power plane, represented by d. This is found by the formula dnt, which in this case makes for a simple calculation!
The capacitance as a function of the number of layers distance (Cd) is found by the formula:
Cd(ε* εr * A * f )/d

Using this formula,

C(l * d)2.073 pF (layer closest to ground/power plane)

C(2 * d)1.037 pF (layer next closest to ground/power plane)

C(3 * d)0.691 pF (layer farthest from ground/power plane)

To find the average capacitance per inch (Cavg), then:

Cavg(C(1 * d)C(2 * d)C(3 * d))/31.267 pF

From this example, it is apparent that the stray wiring capacitance can vary significantly depending on which layer of a multilayer PC board a particular trace is located. Since a signal may travel on different layers between source and destination, exact values might be difficult to determine.

When performing a worst-case analysis of a given design, it is most effective to calculate the total load capacitance based on the sum of the loads’ input capacitances, plus an estimate of the nominal wiring capacitance using 1 or 2 picofarads per inch of wiring using a rough guess for the length of the trace.

In a typical design, we might pick the diagonal distance from one corner of the board to the other and multiply by 1 or 2 picofarads. If the total load capacitance is less than the driving device’s specified test load capacitance, the device will perform as specified.

If not or if it’s very close, we might want to make a more accurate estimate or avoid the problem by using a driving device that has a larger specified test load capacitance. Other alternatives include using two outputs from the same chip in parallel to double the drive capacity or splitting the loads into two separate groups and driving them independently from two different sources.

As digital IC technology has improved, allowing signals to be processed at ever-increasing rates, the other non-ideal effects of the devices that could be ignored at lower speeds become more important. At very high speeds, these secondary effects become much more important. A wire ceases to be equivalent to a 0 ohm connection with zero time delay.

For the newer high-speed logic devices, the speed of the signal traveling down the wire, distributed resistance, and inductance, as well as capacitance, may become very important. When the time it takes a signal to propagate down a wire is of the same order as the rise and fall time of the signal, it behaves as a transmission line rather than an ideal wire. Transmission-line effects are briefl y described later in this article.

Next in Part 3: Fan-out when CMOS drives LSTTL
To read Part 1 , go to Timing is essemtial .

Ken Arnold, the author of Embedded Controller Hardware Design, is Embedded Computer Engineering Program Coordinator and an instructor at UCSD Extension, as well as founding director of the On-Line University of California. Ken was also the founder and CEO of HiTech Equipment Corp., CTO of Wireless Innovation and engineering chief at General Dynamics.

This article  is based on material from “Embedded Hardware know it all,”  used with permission from Newnes, a division of Elsevier. Copyright 2008. For more information about this title and other similar books, please visit www.elsevierdirect.com.

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