Embedded system timing analysis basics: Part 3 – Fan-out when CMOS drives TTL - Embedded.com

Embedded system timing analysis basics: Part 3 – Fan-out when CMOS drives TTL

A common design problem involves the determination of the number of LSTTL loads a CMOS output can drive. In this section, we will use the parameters shown in Tables 6.1–6.4 below to create an example to determine the number of LSTTL loads a CMOS gate can drive.

Table 6.1: LSTTL gate DC parameters.

 

Table 6.2: Absolute maximum operating conditions.

 

Table 6.3: CMOS gate DC parameters.

 

Table 6.4: Absolute maximum operating conditions .

Thus, considering the DC specifications only, the maximum number of loads driven is 10, since the zero state is the worst-case condition. The AC parameters would not be the limiting factor in this case because the CMOS output is specified with a CL of 150 pF, and each LS input is only 10 pF. Thus, 10 loads would present 100 pF plus stray wiring capacitance of less than 50 pF would present an AC load less than the 150 pF CMOS output load-handling capability.

How many additional CMOS loads could be added? There are two levels of answer for this problem. First, from a DC point of view all the CMOS IOL output sink current is used up, so from this point of view, no loads could be added. However, there is negligible current in a CMOS input, so it is not the practical limit.

In fact, the errors in the DC computations above are in excess of the amount required to drive a CMOS input, so in reality the DC current is not a problem. The real limitation is the capacitive loading.

Even if you assume that the loading from the TTL inputs and wiring can be ignored, the CMOS input capacitance will limit the loading. For the output to conform to the specs, the test load was specified as 150 pF (CL).

With 10 LSTTL loads of 10 pF each, the CL on the CMOS gate output would be 10 * 10100 pF. Since the CMOS gate timing is specified at CL150 pF, there is only 15010050 pF left over to drive the additional CMOS loads. Since the CMOS Cin is 25 pF, the number of additional gates that can be driven is:

50 pF/25 pF(remaining CL )/(Cin of additional CMOS inputs)2

Practically speaking, the wiring capacitance on a PC board will generally be in the 2–3 pF per inch range, so allowing 25 pF for wiring capacitance would permit one CMOS load in addition to the 10 LSTTL loads from above.

What if the CMOS output were to drive only CMOS loads? The input capacitance of the CMOS gate is 25 pF, so even if all loads were CMOS, it can only drive CL/Cin150 pF/ 25 pF6 CMOS loads and still meet its test condition limits. Since we must also allow for the wiring capacitance, we should limit this device to five loads, leaving 25 pF for the wiring capacitance.

The additional load capacitance from more than five devices would likely result in timing performance that would be poorer than that specified in the data sheet. Excessive capacitance can also make ground bounce worse, which is the change in on-chip ground voltage due to rapid current spikes caused by charging load capacitance, developing a voltage across the lead inductance of the driving IC.

Transmission-Line Effects

When you’re using high-speed logic and the rise and fall times are of the same order as the propagation of the signal, transmission-line effects become significant. When a signal transi­tion propagates down a wire, it will be reflected back if the signal is not absorbed at the des­tination end. At lower speeds the effect can be ignored, but with the fastest processors now in use, most designers will need to consider whether the effects will have a negative impact on their designs and take appropriate action if necessary.

Several characteristics of digital transmission lines must be addressed, including the following:

• Signal transition time vs. clock rate

• Mutual inductance and capacitance (crosstalk)

• Physical layout effects

• Impedance estimates

• Strip line vs. micro strip

• Effects of unmatched impedances

• Termination and other alternatives

• Series termination vs. parallel termination

• DC vs. AC termination techniques

The techniques for high-speed design are beyond the scope of this text but are covered in detail in an excellent text on the subject, High-Speed Digital Design: A Handbook of Black Magic, by Howard W. Johnson and Martin Graham. In contrast with the subtitle, this subject is easily understood by applying some very basic physics.

A transmission line is a conductor long enough that the signal at the far end of the line is significantly different from the near end, due to the time it takes the signal to propagate from one end to the other.

In this book, we will assume that the interconnections between the devices are not long enough to require transmission-line analysis. To verify that this is the case we can use a simple estimate. The rough estimate we will make is based on the idea that a wire does not have to be analyzed as a transmission line if the signal takes longer to rise or fall than it takes to get from one end of the wire to another.

In other words, if the signal doesn’t have to travel too far, both ends of the wire are at approximately the same voltage. To come up with a numerical value to determine whether a signal must be treated as a transmission line, we can use a simple calculation:

I = Tr /D

where:

I = Length of rising or falling edge in inches (in)

Tr = Rise time in picoseconds (pS)

D = Delay in picoseconds per inch (pS/in)

For traces on a standard printed circuit board, the value for D will be in the range of 100 to 200 pS/in. Depending on how much distortion you’re willing to live with, the critical trace length will be between one-sixth and one-quarter of the length of a trace corresponding to the signal’s transition.

For a trace that is shorter than one-sixth the length of the signal’s rising or falling edge, the circuit seldom needs to be considered to be a transmission line.

Traces that are much longer than one-quarter the length of the fastest edge will start to behave as transmission lines, exhibiting reflections of the signal when the transition gets to the far end of the trace and is reflected back to the near end. Once the trace is about half of the length it takes for a logic transition to propagate, the problems become quite pronounced.

Let’s look at an example. A logic device on a standard glass-epoxy printed circuit board has a 2 nS rise time. This signal has a rising edge that is:

(2 nS)/(150 pS/in) = about13 inches long

That means a trace that is one-sixth that length, or about 2 inches or less, does not have to be considered as a transmission line. If the trace is much longer than two inches, it will begin to show significant distortions on the rising and falling edges due to the fact that there is a different signal voltage at each end of the trace at the same instant, resulting in reflections of the signal from the ends of the trace.

This is one of the most important reasons for using logic that is fast enough and not too much faster than required to meet the timing requirements. Although it might seem tempting to buy the fastest device available to reduce the delays in a device which does not meet the timing requirements, doing so can result in many more difficult problems to solve.

Ground Bounce

Another effect of high-speed signal transitions is called ground bounce. Ground bounce occurs when a large peak current flows through the ground pin of a chip when one or more logic outputs change state and discharge their load capacitances through the chip’s ground pin.

The parasitic inductance of the ground pin might not seem very significant, but in the nanohenry (109 nH) range, fast transients can cause large voltages to appear across the ground pin. This occurs most often when multiple bus signal outputs from one chip change state at the same time.

The rapid, parallel current pulses which result from charging or discharging stray bus capacitance must be carried through the ground or power pins, which have inductance. The voltage across an inductor is equal to the inductance times the rate of change of current through the inductor, or:

VL * di/dt

where:

V = Instantaneous voltage across the inductor (volts)

L = Inductance (henry)

di/dt = Rate of change of current (amperes/sec)

current i = Q/t (amperescoulombs per second)

The charge on a capacitor is Q= CV (coulombs = farads * volts)

V=L * C * (delta V )/(delta t)2

approximately, or:

V  = L * C * (V = Vol )/(Tr )2

using the output voltage and rise time.

Because of the high-speed (nS) and large (amperes) peak currents, even the small nanohenry inductance can induce a voltage transient on the order of volts. (The instantaneous voltage across an inductor is V = L * di/dt.) For typical high-speed signals, nanohenries * amperes/ nanoseconds= volts!

This effect is minimized by the use of minimum circuit interconnect trace lengths, wider ground traces, power and ground planes, and small, surface mounted IC packages that have very short leads.

For example, a CMOS output driving a 100 pF load with a rise time of 2 nS would induce a voltage across a typical 1 nH inductance of the chip’s ground lead:

V = 1 nH * 100 pF * (4.5 – 0.5 V)/(2 nS)2 =0.1 V

Although a voltage of 0.1 volt or 100 millivolts may not seem like much, remember that a part with many outputs, such as a processor, will sometimes switch many outputs at the same time, and the current that fl ows through those pins all has to fl ow through a single ground pin. An 8-bit output will cause 0.8 volt pulse or ground bounce.

If the processor drives an 8-bit data bus and a 16-bit address bus low at the same time, this would result in a 2.4 V bounce! The ground bounce voltage across the ground lead inductance results in a different ground voltage reference for the chip while the chip’s ground is bouncing. Needless to say, this ground bounce can cause a logic level to change during the brief pulse, which can cause trouble with circuits, such as clock signals, which are edge sensitive.

This is why high-speed logic devices may have multiple, short ground pins and may only be available in small, surface-mounted packages. To make things even worse, if two devices overlap slightly in time driving the bus, very large current transients may briefly generate even larger currents that in turn generate larger ground bounce pulses. This can disturb several chips on the board at the same time.

The power supply leads are also subject to bounce for exactly the same reasons, and even though the power supply is not used as a logic voltage reference, the resulting drop in the local power supply voltage to the chip can result in errors.

Exact ground lead inductances may prove difficult or impossible to measure, but there is always some inductance in the ground lead, and the longer the lead, the greater the inductance.

The example above illustrates another reason that it makes sense to avoid logic that is faster then necessary and to use very short ground and power wires. In fact, high-speed PC boards should use separate inner layers of a multilayer board to provide large ground and power planes, allowing the chips’ power and ground leads to be connected using very short wires.

The magnitude of the bounce depends on the number and direction of logic transitions, so the noise is also data dependent. This is an apparently intermittent hardware design fault with symptoms that act like a software bug, since it might only happen at certain points in executing a program, with certain data values.

The example also shows why it is so important to maintain sufficient tolerance to noise in the logic. This noise tolerance is referred to as noise margin, which is covered in the next section. Noise margin analysis is especially important in a high-speed logic design, to prevent transient logic errors, which are extremely difficult to track down. This is another example of how a proper analysis and worst-case design can save a lot of time and money while delivering much higher quality and, ultimately, reliability. Next we get into some examples of the noise margin analysis and worst case timing analysis processes..

Next in Part 4:Doingnoise margin and timing analysis
To read Part 1 , go toTiming is essemtial
To read Part 2, go toFan-out & loading analysis
Ken Arnold, the author of Embedded Controller Hardware Design , is Embedded Computer Engineering Program Coordinator and an instructor at UCSD Extension, as well as founding director of the On-Line University of California. Ken was also the founder and CEO of HiTech Equipment Corp., CTO of Wireless Innovation and engineering chief at General Dynamics.

This article  is based on material from “Embedded Hardware know it all,”  used with permission from Newnes, a division of Elsevier. Copyright 2008. For more information about this title and other similar books, please visit www.elsevierdirect.com.

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