To illustrate some of what we have been talking about so far in this series, here are two design examples, one for a noise margin analysis spreadsheet and the other for timing analysis
Building a noise margin analysis spreadsheet
The spreadsheet in Table 6.5 below shows the results of a noise margin on a design that was already in production at the time of the analysis. The product’s users had complained about intermittent glitches, and the author was consulted to determine the source of the problem.
Table 6.5: 8051 Noise Margin Analysis Sample .( To view larger image of this analysis click here)
After a quick look at a few of the noise margin values, it became obvious that there were deficiencies in the design in that area. A portion of the spreadsheet used in that analysis is shown in Table 6.5, with problems shown in bold italic underline font.
The first column of Table 6.5 is the signal name, followed by the pin number and chip that is the source of the signal, followed by the source’s worst-case output voltages, Volmax and Vohmin. The next columns list the loads on the signals and their respective worst-case input voltages Vilmax and Vihmin.
The noise margins are shown in the last two columns, Vil–Vol for the logic zero case and Voh–Vih for the logic one case. As shown, the logic zero noise margins are all probably acceptable, since the lowest value is 0.3 V. The logic one noise margin is zero or negative for most of the devices listed, which is completely unacceptable.
Any noise on the power supply, ground, or the signal lines themselves can easily cause a logic input to interpret the wrong logic state, causing an error. An interesting thing to observe is that none of them were very far out of spec, and the instrument worked perfectly most of the time.
These problems can be virtually impossible to find in the field. Hooking up a test instrument like a scope or logic analyzer to the problem signals often makes the problem go away due to changing the ground currents and impedances of the circuit. The specs that cause the problem in this case are the high Vih specs of the loads, especially the SRAM chip.
The example design in the spreadsheet represents a relatively common problem with devices that are advertised as “compatible” with other logic families. The solution to the problem is very simple and inexpensive: the addition of pull-up resistors to the signals that have zero or negative noise margin in the logic one state.
This also impacts the output low current that must be handled by the signal source chip outputs, so it must be taken into account in the load analysis, and pull-up resistors should be chosen accordingly.
It is important to note that there are four sources listed for AD0 .. 7, since there are four devices that drive the data bus. Only the data paths that are used need to be evaluated vs. loading analysis, where unused paths load the bus.
The load analysis for another similar design is shown in Table 6.6 below , which tabulates the capabilities of the various driving devices and the loads that are presented to them. The ﬁrst three columns (signal, pin, and source) identify the signal source; the next three (IOL, IOH, and CL) list the corresponding source’s output drive current and capacitive load values.
The next two columns (load, and signal) identify the load’s signal names. The Qty column is the number of loads in the case of multiple signals connected to the same output or the number of inches of wire in the case of the wire capacitance.
The next three columns (IIL, IIH, and Cin) deﬁne the load characteristic of a single input’s input current and input capacitance. For the interconnect wiring, Cin is the estimated stray wiring capacitance per inch of the printed circuit trace.
The last three columns show the extended totals and grand totals for each signal, followed by the design margin, which should be a positive number. In this case there is only one problem, due to excessive capacitive loading of the SRAM when it drives the data bus, AD0 .. 7.
The output capacitive load specs are usually found as notes within the AC section of the chip speciﬁcation listing the various timing parameters. This is because the capacitive loading affects the rise and fall time of the signal, so the capacitance value is really used as a test condition for the timing measurements.
Input capacitance may be difﬁcult to ﬁnd in the speciﬁcation sheet, it might be in a different “family” speciﬁcation sheet or handbook, or might not be speciﬁed at all. When it is not speciﬁed, a reasonable estimate can be made by substituting values for similar parts in the same type of package.
The SRAM output is speciﬁed with a Cload value of 50 pF, which is relatively low value. By using a very low load capacitance, the SRAM’s timing specs look good due to shorter than normal rise and fall times, since the chip is not driving a realistic load. This is a good example of a manufacturer’s “specsmanship.” They are intentionally playing games with the test conditions to make their device appear to be better than it is.
That way. when someone looks at their timing specs, the shorter rise and fall times make their chip appear to be faster than another equivalent chip that is speciﬁed with a larger capacitive load value when the chips are actually identical. Unfortunately, this practice is all too common, so the designer must view the claims on the cover of a data sheet very critically. If it looks too good to be true, then it probably is!
When an output like this is operated with actual capacitive load greater than the test conditions, the related timing specs for the device must be de-rated due to the degraded rise and fall times that will occur. As long as the load capacitance is no more than twice the spec value, this will be sufﬁcient.
The excess C load will increase the stress on the driver. If the overload is much greater than two times normal, the device can be overstressed due to the relatively large currents that will ﬂow into the load capacitance on transitions when the C is charged and discharged through the driving output.
As long as the output is not overloaded too much, the resulting increase in the rise/fall time can be estimated, resulting in a de-rated timing spec. All we have to do is calculate the additional rise time and add that to the timing values specifiedin the data sheet. To do that, we need to evaluate the output circuit’s performance.
This can be accomplished by noting that the output current drives the load capacitance from a logic low to high or vice versa. For our purposes, we will assume that the interconnect does not behave like a transmission line, which is most often the case for garden variety microcontroller components.
If the chips used have a fast rise time and trace length greater than about one-sixth the edge length of the pulse, it is necessary to analyze the circuit as a transmission line. In this case we will look at the simpler problem.
By assuming a constant current charging the capacitance, the voltage will ramp linearly from one logic level to the other. To make a rough estimate, we can use the source’s output current and load capacitance to determine the signal slew rate and the difference between the high and low logic levels to determine the delay. Figure 6.14below illustrates this idea.
Figure 6.14: De-rating delay for excess CL .
Let’s next look at a simple example showing how to de-rate the timing based on the approximation technique just described.
First we make the assumption that the signal timing measurements in the data sheet are made under the speciﬁed test conditions, usually with the output loaded by RL and CL in parallel to ground. The output delay speciﬁcations in the data sheet include the internal delay as well as the rise time.
The output drive current charges CL within the speciﬁed time. The circuit can be divided into two parts: the speciﬁed load, and the additional output current available to drive the excess load C. So the additional delay (delta T) we are looking for depends upon the leftover drive current (delta I) which is available to charge the excess load capacitance (delta C). The equation for this is:
Delta T = (delta V * delta C)/(delta I)
Let’s look at a typical example. An SRAM is speciﬁed with a 50 nS access time, but the outputs are overloaded with respect to the CL spec in the data sheet. What access time spec should be used for the actual conditions specified below?
• The output is speciﬁed to drive CL50 pF, but the actual load is 100 pF.
• The output is speciﬁed to drive 20 mA into the load, but the load is only 10 mA.
• The driven device has input voltage specs Vilmax0.4 V, Vihmin3.4 V.
So in this case 15 nS should be added to all the output delay specs for the driving device. The access time used should be:
Taa(actual) =Taa(spec) + (delta T)50 nS + 15 nS = 65 nS
Since the output current from most devices is larger at the beginning of the transition and smaller near the end of the transition, the approximation is only a rough guide. Also, the delta V calculation is conservative, since the input threshold voltage is typically halfway between the Vih and Vil values.
So, the estimate as shown will usually be conservative compared to actual performance. All of the above must be used with caution and is only an approximation of the additional delay caused by excess CL, so it is wise to allow additional margin in the timing for any de-rated specs.
Here’s another typical example. An LSTTL gate is to be used to drive one LSTTL load and a CMOS processor clock input, as shown in Figure 6.15 below . An interface must be made which will guarantee the CMOS input voltage requirement will be met with the same noise margin as a standard LSTTL input. The LSTTL and CMOS gates have the specs as defined below:
Figure 6.15: TTL-to-CMOS interface example.
Here is how we would determine the answer. Since the LSTTL VOL is 0.4 V and the CMOS VIL is 2.0 V, the CMOS input low voltage is compatible with the LSTTL low output voltage, shown in the table below .
Absolute maximum operating conditions
However, the LSTTL output high voltage of VOH2.8 V is not sufﬁcient to meet the CMOS input high VIhmin 3.0 V. A pull-up resistor is required to allow the LSTTL output to go to a higher voltage, VIH = Vnoise margin = 3.0+ 0.4= 3.4 V. There is no exact solution, but the range of resistors meeting the requirements can be determined.
The lowest resistor value that will work is the value which will source enough current so the LSTTL output is just able to sink the resistor current plus the additional LSTTL load when the signal is low and still meets the maximum output low voltage speciﬁcation. Negligible DC current is ﬂowing from the CMOS input.
The voltage across the resistor is Vcc – VOLmax . for the LSTTL input, or 5 – 0.4 = 4.6 V. The current required is IIILmaxIRPU where IILmax is the current coming from the LSTTL input load and IRPU is the current ﬂowing through the pull-up resistor. The current the LSTTL output must sink is the sum of the IIL of the LSTTL load and the current through the pull-up resistor.
The equation is:
IOLmin >= IILmax + IRPU = 360 µA(Vcc – VOLmax )/Rmin
Solving for Rmin:
Rmin > (5 – 0.4 volts)/(3.2 mA – 360 µA) = 4.6 V/2.84 mA = 1.62 kilohms
Rmin is 1.62 Kilohms
This value is also greater than speciﬁed as a test load of 1 kilohms. The maximum acceptable value, Rmax, is determined by the minimum output high voltage that will guarantee a CMOS high input plus noise margin.
The resistor must be able to supply the LSTTL maximum input high current and not have too large a voltage drop across it. This will determine the upper limit for the resistor value.
Speciﬁcally, the resistor voltage is:
Vcc – (CMOS VIH min + Vnoise margin ) = 5 – (3.0 0.4) = 1.6 volts
This voltage is maintained while sourcing the LSTTL Imax of 60 µA. Solving for Rmax:
Rmax = 1.6 V/60 µA26.7 kilohms maximum
Thus, the acceptable range for the pull up resistor is:
Rmax <=, 1.62 kilohms<= Rpu <=26.7 kilohms
An acceptable standard value such as 10 kilohms would be appropriate.
Another limit relates to the rise time of the signal under load, due to the R-C time constant of the pull-up resistor charging the load capacitance, CL. From the example above, let’s see what the effect of this time constant is on the selection of the resistor value.
The maximum R value can be approximated by the equation:
R = T/CL
where T is the rise time and CL is the total load capacitance.
Ignoring the Ioh current of the LSTTL driver, if the circuit above had an allowable rise time T= 50 nS and CL = 20 pF, then the maximum R value would be:
Rmax= 50 nS/20 pF= 2.5
kilohms maximum to maintain the 50 nS rise time.
So a better choice might be a standard 2.2 kilohm pull-up resistor. Since the driver will supply some current to charge the load capacitance, this is a fairly conservative value. We would also have to allow for the additional rise time as part of the timing analysis for the low-to-high transition.
Worst-Case Timing Analysis
Let’s suppose an LSTTL gate is used to enable the D input of a flip-flop frequency divider, as shown in Figure 6.16 below :
Figure 6.16: Example of worst-case timing .
Figure 6.17 below shows a functional timing diagram for the circuit in Figure 6.16, and Figure 6.18, also below , illustrates a speciﬁcation timing diagram for the same circuit.
Figure 6.17: Functional timing diagram for Figure 6.16 .
Figure 6.18: Specification timing diagram for Figure 6.16.
The timing of the input signals must conform to the combined specs of both devices, as deﬁned in the tables below :
For the circuit shown in Figure 6.16 and the accompanying speciﬁcations, what is the maximum guaranteed clock rate?
From the timing ﬁgures above, note that the minimum clock cycle time is deﬁned by the sum of the following times: the time it takes for the transition from the active edge of the clock for the signal at D to propagate through the flip-flop through the NAND gate and the time the signal must be stable before the next clock. The maximum propagation times and minimum setup times are used as they are the most severe requirements.
TPCKQ + TPLH + TSU =15+6+ 10 = 31 nS
f = 1/t = 1/31nS= 32.26 MHz
Now let’s determine the setup and hold time requirements for the overall circuit. The overall setup time is lengthened by the delay of the NAND gate; therefore, the system setup time is the sum of the flip-flop setup time and the worst-case propagation delay.
TSU (system)= TPLH – TSU (ﬂip-ﬂop)= 16 nS minimum
For the overall system hold time, the hold time of the flip-flop is offset by the minimum delay through the NAND gate, since this is the minimum amount of time that can be counted on to delay a changing D input to the ﬂ ip-ﬂ op.
TH (system)= TH (ﬂip-ﬂop) – TPHL (min)= 1 – 1 = 0 nS
The delay in the D signal path reduced the hold time requirement from 1 nS to 0 nS, meaning that the input can change at the same time as the clock edge or later. This is actually an improvement on the performance of the flip-flop by itself, which requires that the D line be held stable for 1 nS after the clock edge.
Ken Arnold, the author of Embedded Controller Hardware Design, is Embedded Computer Engineering Program Coordinator and an instructor at UCSD Extension, as well as founding director of the On-Line University of California. Ken was also the founder and CEO of HiTech Equipment Corp., CTO of Wireless Innovation and engineering chief at General Dynamics.
This article is based on material from “Embedded Hardware know it all,” used with permission from Newnes, a division of Elsevier. Copyright 2008. For more information about this title and other similar books, please visit www.elsevierdirect.com.