As technology progresses, the electronics industry continuallyreinvents itself. Embedded systems designers know this story well, manyhaving developed applications across generations of evolvingelectronics technology and microprocessors.
Along the way, as basic hardware and software have evolved, sotoo have the methods for developing and debugging systems. Today, mostmicroprocessors incorporate on-chip debug resources that enable the useof a low-cost hardware interface for development and testing. This typeof debugging, called embedded test , is significantly aiding thegrowth of embedded systems and will make designing systems withhigh-speed serial I/O more efficient.
The economics of silicon is now making it possible for theelectronics industry to take advantage of some of the advances made inthe communications industry over the past 30 years, specifically theuse of serial interfaces. As digital systems struggle to keep pace withthe bandwidth of optical systems for the large-scale, high-speed datatransmission, the ever-increasing need for speed and overall processingthroughput has driven the evolution of parallel-bus structures to theirpractical limits. To gain more processing bandwidth, the PC industry islooking at high-speed serial interfaces, evidenced by the rapid growthof bus standards like PCI-Express.
As the PC industry adopts serial interfaces, thesetechnologies are becoming more accepted and entrenched. Implementationcosts start dropping, which means serial interfaces are now makingin-roads into lower-cost PC products and mainstream digitalproducts–in other words, embedded systems. Once again, we see thatevolutionary process: as embedded systems and their associatedmicroprocessors pick up the new technology, design teams must adopt newdevelopment and debug methods to take advantage of high-speed serialinterfaces.
Most of today's digital designers are still accustomed to working withparallel buses and system clock speeds around 100 to 200 MHz.Well-developed standards, practices, and tools support such choices.However, high-speed (multi-gigabit) serial is another matteraltogether. Design teams who successfully deploy high-speed serial areoften now employing engineers with specialized skill sets focused onthe physics of high-speed signal transmission (signal integrity). Whilethis approach helps get products to market successfully, moredevelopment team changes are needed to successfully incorporate thisadvanced digital technology into designs destined for the mainstreamdigital electronics market. Teams need more knowledgeable designersalong with the necessary tools and methods to handle this verydifferent type of design problem.
The first step is to understand the design problem. How doesdesigning a digital high-speed serial interface differ? Perhaps themost significant difference is signal integrity. As the signal rates ofkey interfaces move into the gigabit range, behavior occurs that hastypically been the realm of the analog (or more likely RF/microwave)designer. Rather than being concerned about signal timing parameters,such as set-up-and-hold and rise time, designers must deal withparameters such as eye opening, bit-error ratio, and jitter.
Also different is the ability to probe the signal one wishesto observe. This is a function of both the high integration levels seenin today's silicon as well as the need to manage the integrity of thesignal path very carefully. As speeds rise above 3 Gbits/s, it becomesnecessary to apply pre-transmission conditioning to the signal tocompensate for the transmission medium's lossy effects; handling thesignal at the receiver thus requires the corresponding filtering toaccurately recover the signal. Also, because these signals oftenoperate in the low-power environments of sub-micron digital silicon,voltage swing is small. This means that simply attaching a physicalprobe, in traditional test and measurement fashion, becomes virtuallyimpossible because the probe itself significantly disrupts the signal.
Testing and debugging these interfaces must allow for thereal-world effects these factors create. The need to focus on signalintegrity indicates that digital designers must incorporate newmeasurement types (and tools) into their standard tool box of teststhey use to validate these designs. Sophisticated tools that measuresignal integrity and characterize things such as eye metrics, bit-errorratio (BER), and jitter tolerance are becoming more common and mustevolve from their once-specialized role into more mainstream offerings.Approaches must evolve to allow for probing these critical signalsgiven their sensitive nature and the high integration levels seen intoday's silicon implementations.
Embedded testis the answer
As with the emergence of on-chip debug tools and techniques in themicroprocessor world, the answer, at least to the probing problem, isto implement more of the test functions in the silicon itself. Becausethe signal path is by definition managed carefully by the chipdevelopers, incorporating the ability for the application designer tomake key measurements and observe the serial interface's behavior canbest be handled in this way. This method, called embedded test,eliminates the need to attach an external probe (with its associatedproblems) and allows access to information about the signal (such asthe actual eye metrics recovered by the receiver) that wouldn't beavailable externally.
A real example of this is shown in Figure 1. Here,measurements made on a serial link operating at 6.25Gbits/s show thateven if physical probing limitations can be overcome, observing thesignal at the device's pins yields confusing information due to theapplication of pre-transmission signal conditioning. Simply by lookingat just this information, one might conclude that the link isn'toperating because no signal eye can be observed. However, byincorporating on-chip measurement, as seen in the view on the right ofFigure 1, engineers can determine that a signal is indeed beingrecovered by the receiver.