Embedding custom real-time processing in a multi-gigasample high-speed digitizer - Embedded.com

Embedding custom real-time processing in a multi-gigasample high-speed digitizer

Real-time data processing after analog-to-digital conversion at multi-gigasamples per second on digitized data can't be performed on a host computer as the backplane is not fast enough to extract the samples at full speed. In addition, a modern multi-processor workstation can't perform real-time operations at such rates. Hence, an FPGA with enough available resources for customization inside the acquisition module is the ideal solution to apply such real-time algorithms on the acquired data at full speed.


Figure 1. The FPGA is the ideal place to host a custom real-time algorithm operating at multi-gigasample per second (Source: Keysight Technologies)

Reducing the amount of data produced, accelerating the algorithm's execution, and improving the software application processing and analysis time are among the main reasons why a programmable device open for customization on the digitizer data path is required.

Furthermore, confidentiality is a sensitive topic, especially for aerospace and defense (A&D) applications and new wireless communication standards like 5G. An FPGA with modern encryption techniques is the ideal place to protect intellectual property (IP).

Engineers will come across a variety of alternative solutions if they wish to implement real-time data processing on a signal acquired with a high speed digitizer. Some of these solutions offer a basic approach providing strictly the minimum set of capabilities to customize the FPGA with limited or no support. Others have a more comprehensive approach providing everything that is required to quickly turn ideas into reality, including access to the full features and performance of the digitizer coupled with an extensive engineering service.

Hidden and upfront costs, time to market, guarantee of success, and continuous support are key elements in choosing between solutions.

Key elements of a modern FPGA development kit
Nowadays, most high-performance, high-speed digitizers share the same analog-to-digital converter (ADC) technology and include an FPGA with direct access to the acquired samples and to the onboard memories. As was previously noted, embedded real-time processing is required, allowing data reduction and storage to be carried out at the digitizer level. The overall benefits are minimizing data transfer volume, speeding up analysis, protecting IPs, and enabling new applications. Unfortunately, few digitizer manufacturers open the FPGAs of their digitizers by offering a special tool to facilitate custom firmware development.


Figure 2. A typical architecture for a FPGA based digitizer card
(Source: Keysight Technologies)

There are several key elements designers should pay attention to before making their choice concerning the hardware, the design environment, and the software.

Sharing the same ADC and FPGA hardware technology doesn't mean achieving the same level of performance. Overall performance might vary greatly from one manufacturer to another depending on additional proprietary integrated circuit devices onboard, the front-end design, calibration features, and the qualification and test process.

In order to meet aggressive time-to-market goals and minimize the risks associated with a project, engineers should expect at minimum the following from an FPGA development environment:

  • A pre-configured environment, thereby saving the time-consuming effort of selecting the tools, adapting constraints and scripts, and verifying the flow.
  • A database of optimized and standardized cores, which — coupled with a stable and reliable design flow — ensure fast compilation times and repeatability of results.
  • A functional system-level testbench environment allowing quick verification of the custom algorithm integration before running the building flow.
  • An automatic flexible and configurable building script to ease repetitive tasks, thereby allowing users to produce multiple bitfiles every day.
  • A direct line of support to an FPGA and digitizer expert who can address any issue and consult on the best approach to implement the algorithm(s) to assure the success of the project.

The software driver should offer a standardize API interface, support for multiple and modern languages like Python, a dedicated custom interface, and a reusable calibration routine. Such a driver reduces the need for detailed hardware knowledge of the common control functions, enables fast and easy integration of custom processing, and avoids erroneous operations by protecting against prohibited actions.

Additionally, a suite of complete example designs and an easy design migration path facilitating deployment on multiple products and form factors with small delta effort is also of great benefit.


Figure 3. A standard FPGA design flow; the grey areas represent processes that should be automated. (Source: Keysight Technologies)

All together, such a solution would allow real-time custom algorithms to be quickly designed, verified, implemented, and deployed with a significant reduction in development time.

Upfront costs, hidden costs, and time to market
When it comes to embedding an algorithm in a high speed digitizer, the selection of the hardware and associated development environment has a great impact on the time to market and total cost of ownership. The initial price paid by the user for accessing the FPGA's programmability may represent only a fraction of the total final cost for deploying a custom solution. Each hour of R&D engineering spent in creating, optimizing, and automating the design flow, trying to achieve the desired analog performance, or waiting for customer support detracts from the algorithm's design time. These hidden costs add to the initial price of the selected solution, negatively impacting the time to market for the final product, hence delaying sales revenue.

EDA tools and repeatability of results
In a standard FPGA development environment, many elements need to be configured and validated in order to interface with the hardware. The FPGA flow necessary in order to generate a bitfile can be complex and a broad range of knowledge in the digital design domain is required. EDA tools can be difficult to configure and their usage and behavior might differ from one version to another.

Including state-of-the-art tools and associated licenses in an FPGA development kit comes with a cost for the user, but also with many advantages. There is no more need to spend engineering time configuring and sorting out the best configuration to achieve the desired results, or having to repeating this for each new version. In addition to having a standardized flow, a well-designed flow provides functional partitioning and optimized locked floor planning that guarantees repeatability of results and eases support. Furthermore, tools offered as part of an FPGA development kit bundle often come with significantly reduced prices for the end user as compared to buying the same tools directly from EDA providers. This automated process allows engineers to concentrate on the algorithm design, thereby reducing time to market and final development costs.

Calibration and analog performance
Calibration of the instrument is essential in order to achieve the performance advertised on the digitizer datasheet. Combining this performance with the ability to embed custom processing is challenging but very important. Alternatively, end users could implement their own calibration routines, but nowadays this represents a nearly impossible and extremely time-consuming task as it requires mastery of many hardware details related to the selected platform.

Ideally, users should be able to calibrate the board with their custom bitfiles in a seamless manner — irrespective of which functionality they have implemented — and still achieve the level of performance reported in the datasheet. One effective approach is to provide — with any custom FPGA image — the infrastructure required to execute the software calibration routine provided in the API, thereby allowing the user to work at the FPGA level on the calibrated data. As an additional advantage, the digitizer function should always be available and accessible by the user on board the acquisition card, irrespective of whether it's being used with a custom or standard bitfile.

Support, debug, and training
What happens if an engineer comes across an issue while using an FPGA development kit? Even if automation is provided and the complexity of the hardware is masked, designing and deploying an algorithm into an FPGA remains a specialized R&D task and — as such — should be supported by an expert both on the hardware description language (HDL) and the hardware. Otherwise, it may take weeks to figure out the issue and solve it, thereby negatively impacting the schedule and resulting in loss of revenue.

Hardware debug is also required when deploying an algorithm into a digitizer. All major players in the FPGA market today offer the ability to insert virtual logic analyzers into their devices, allowing view of any internal signal or node. Signals are captured at the speed of operation and brought out through a JTAG debug interface. Captured signals are displayed and analyzed using the debugging analyzer tool. An FPGA development kit should offer these in-circuit debug capabilities to the users along with an easy-to-access standard connector. Finally, training sessions might be required in order to bring the engineer(s) working with the FPGA development kit up to speed. This is particularly applicable to the OEM market in which the hardware or multiple cards are intended to be customized and deployed in final measurement instruments.

Introducing the Keysight U5340A FPGA development kit
This design tool is an example of a commercial solution for the implementation of custom algorithms across the entire family of Keysight high-speed digitizers in PCIe, AXIe, and PXIe form factors. It provides an integrated and automated environment with predefined capabilities and includes powerful design engines from Mentor Graphics and Xilinx. Those engines are all linked together and interact with the pre-designed building flow.

The U5340A enhances design efficiency and can reduce development time by months as uses can leverage the same proven development environment used internally by Keysight R&D teams. It eliminates the time required to set-up and to configure the tool and allows access to the full resources and processing capabilities of the hardware. The “Get Started” design example allows users to start faster with a design template and to build an initial custom design in just one hour. Premium customer service direct from engineering ensures the feasibility and success of the user project.


Figure 4. Comparison of FPGA development time: standard versus Keysight U5340 FPGA development kit (Source: Keysight Technologies)

The U5340A can currently be used to develop custom algorithms with high-speed digitizers from 8 to 12-bit resolution and 1 to 4 GS/s sampling rate.

For very demanding high-channel count applications requiring numerous real-time interfaces, the M9703B-B01 enables up to 192 programmable front-panel IOs with fixed low latency.

The U5340A FPGA Development Kit shortens the customer time-to-market with turn-key, easy-to-use development flow and debug and facilitates configuring the custom real-time processing area of the FPGA within a high-speed digitizer. It combines capabilities to achieve multi-gigasample real-time processing on a full digitizer framework by leveraging the full density and speed of the FPGA.

Click Here for more information about the U5340A FPGA development kit and other products and services from Keysight Technologies.

Leave a Reply

This site uses Akismet to reduce spam. Learn how your comment data is processed.