Graphics display controllers (GDCs) are the central engines ofautomotive infotainment systems, including head-end units and fullyconfigurable instrument clusters that require versatile human/machineinterfaces.
Originally designed for navigation systems in high-end vehicles inthe Japanese and European markets, GDCs are now found at the heart ofmidrange and lower-end models worldwide.
An automotive GDC combines many functions required in the carenvironment. A GDC's principal function is to control the LCD panelwhile producing a wide range of rich graphical content.
The GDC can enable advanced functions such as point-of-viewnavigation, realistic representations of analog gauges, vibrant splashscreens and other animations that are possible without placing too muchpressure on the main CPU. Additionally, a GDC will perform at powerlevels that make external cooling components such as fans or heat sinksunnecessary.
|Figure1. Along with the memory interface, the the 32bit MB86296 GDC fromFujitsu has a CPU, video capture and video output interfaces.|
Unlike desktop graphics controllers, a GDC designed for embeddedapplications is used with smaller screens of lower resolutions.
Automotive displays are typically limited to resolutions that rangefrom CIF (320 x 240) for basic information displays to Ultra Wide VGA(1,024 x 480) for instrument clusters. Considering the amount ofinformation that may be displayed on these small screens and the needto present the information very clearly, the vehicle environmentpresents some specific challenges.
GDCs use multiple layers and a variety of transparency options thatallow the viewer to have several screens visible at one time. Screenscan be resized and moved around the display area similarly to a Windowsdesktop system. The GDC will allow the viewer to see underlying screensor icons, thus improving the efficiency of the display.
As with MCUs, GDCs come in many types and performance levels. There arefive different categories of performance. A basic GDC includes a simpleframe buffer memory and a controller to generate the display signal.The host controller handles the drawing function while manuallymodifying the display frame in the buffer.
A more complex version includes the frame buffer and a drawingengine with basic 2D functions, such as line drawing and polygondrawing. This kind of GDC may overlay two or three layers whileperforming alpha blending between them.
The third level of complexity is found in a GDC that overlays asmany as four to six layers. This level of IC implements both alphablending and alpha plane functions with hardware cursors, and includesfull-featured drawing functions.
A fourth category of GDC adds the following capabilities: a 2D/3Dgraphics engine along with a geometry processor and a drawing enginethat operate at internal frequencies of 100- 200MHz—which provide ahigh drawing rate – and can reach 400MHz for display dot clocks.
|Figure2. An SoC combines the host CPU and GDC into one chip using ahigh-speed data channel for high-bandwidth CPUGDC communication.|
Finally, advanced GDC versions such as the 32bit Fujitsu MB86R01provide additional multimedia functions, including A/V support with theability to decode A/V rather than just capture and resize it, which isthe process for other categories.
Fogging, lighting and programmable shading functions are alsoincluded in this advanced version, delivering dramatic and realisticeffects with a high and fast draw rate.
In selecting a GDC, it is also important to determine how much, ifany, of the processing will be passed to the CPU. If the host processoris capable of 400MIPs or more and there will be a significant number ofcycles available, then it's possible to use the CPU for executinggeometry operations and use a simple GDC for bitmap operations.
On the other hand, if the main processor does not reach high levelsof instructions per second, then a powerful GDC provides the solution.The main processor must be fast enough to keep the GDC fed with bitmapcoordinates and display lists so that there is a level of relativitybetween processor and GDC that must be considered. Choosing a processordepends on the complexity level of the graphics or images to bedisplayed.
Regardless of the category, the ICs must perform all of theirfunctions while consuming as little power as possible. Many of thenewest and most efficient versions consume less than 2.3W – far belowthe requirements of earlier versions. GDCs are under constantimprovement for efficiency and performance.Memory is key
Graphics memory is one of the most important components in the GDCsystem. While it is up to the geometry and rendering engines to executethe drawing efficiently, the graphics memory provides the buffer zoneswhere all graphics information is retained.
The display frame to be shown on the panel in a vehicle is stored inthe graphics memory. It is critical for the frame data to be deliveredin a timely and reliable manner to the video output interface.
|Figure3. An SoC combines the host CPU and GDC into one chip using ahigh-speed data channel for high-bandwidth CPUGDC communication.|
A list of different types of data stored in the graphics memoryinclude Drawing Frames; Display Frame, which is a subset of the drawingframe; Z-Buffer Data, with information needed for 3D drawing; VideoCapture Buffer, a 16bits-per-pixel area where data from the video inputinterface is stored temporarily; Polygon Drawing Flag Buffer, whichcontains 1bit per pixel of information that is required while drawingpolygons; and Display List Buffer, Texture Map, and Cursor Patterns.
With such a large variety of information stored in graphics memory,the tasks using this information have to be prioritized for memoryaccess as follows:
1. Display frame refresh
2. Video capture
3. Display processing
4. Host CPU access (for displaylists, texture maps and bitmaps)
5. Drawing access (e.g.Z-buffer and polygon flag buffer).
The display frame refresh updates the display panel's contents 50 or60 times a second. This task requires transfer of a significant amountof data, which directly affects the human-machine interactivity.
Thus, it has to be assigned the highest priority. Video capturebuffers the input video data in the graphics memory. Display processingincludes different processes related to the display controller – e.g.display alpha blending, overlaying and cursor pattern processing.
Host CPU access includes transferring display lists, texture mapsand bitmaps to the memory. The last step is drawing access, whichinvolves updating the drawing frames using the Z-buffer and polygonflag buffer.
Large quantities of data travel across the graphics memoryinterface, so the bandwidth requirement for this interface is high. Atypical GDC has a graphics memory bandwidth of 532Mbps.
However, one memory read/write takes multiple clock cycles, soeffective bandwidth may be onehalf to two-thirds of this value,assuming a memory clock frequency of 133MHz and a data bus width of 32.Advanced GDCs have a memory bandwidth twice this value, or almost1Gbps. The increase in the memory bandwidth of advanced GDCs is enabledby DDR-SDRAM technology. Along with the memory interface, the GDC has aCPU, video capture and video output interfaces.
Most of the data moves across the memory interface. Display lists,bitmaps and texture maps are transferred from the CPU to the GDC. TheCPU might also need to access the GDC registers or memory directly.However, all these tasks do not generate a significant volume of data.In the case of a PCI host interface (33MHz), the GDC typically has abandwidth of 50Mbps.
On the other hand, an SRAM-style host interface has a bandwidth ofmore than 100Mbps. This value depends on the bus clock frequency.Similarly, the bandwidth requirements for video capture and videooutput interfaces are low compared with the memory interface.
These interfaces are dedicated to specific tasks, with data flowinginto the video capture interface and out of the video output interface.Thus, the memory interface is the biggest bottleneck in the entire GDCsystem. Its architecture depends on the target application of the GDC.
Optimized for performance
The memory interface needs to be dedicated. Assigning non-graphicstasks to the memory, such as using a portion of it as the host CPU'swork area, compromises the bandwidth and directly affects the GDC'sperformance. Such a compromise has to be avoided to boost performance.This approach isolates CPU memory from the graphics subsystem.
The system requires separate memory for the GDC and more PCB spaceto accommodate that extra component, but it does deliver the graphicsperformance. Another approach is to unify the memory architecture sothat the host CPU and GDC share a single unit of memory.
If the system uses separate ICs for processing and graphics, thememory interface must be implemented in either the CPU or the GDC. Forthe IC lacking a memory interface, memory data traffic has to be routedthrough the interface connecting it to the second IC.
A better way to implement this architecture is to use an SoC,combining the host CPU and GDC into one chip using a high-speed datachannel in the SoC for high-bandwidth CPU-GDC communication.
This interface is easier to implement inside a chip rather thanoutside it, satisfying bandwidth requirements and space constraintssimultaneously without sacrificing GDC performance. With today'sprocessing techniques, it is possible to develop such SoCs atreasonable cost.
Dan Landeck is Senior Marketing Manager, Embedded SystemsGraphics Display Controller Products, Solutions Business Group, Fujitsu Microelectronics America Inc.