It is crucial to understand the impact of decoupling, in term of power distribution network (PDN) impedance on simultaneous switching noise (SSN) and electromagnetic compatibility (EMC). A PCB with poor power integrity or decoupling, e.g., high PDN impedance, gives rise to the issue of SSN and EMC. The next section of this article showcases the practical work that proves the relationship between PDN impedance, SSN, and EMC of PCB.
Analysis and results
Two versions of the following prototype are tested: An FPGA with external 50MHz reference from crystal oscillator, and three major interfaces: DDR2 SDRAM at 350MHz clock rate, ADC data bus at 150MHz, and Ethernet at 100MHz. All these components draw power from a 1.8V buck converter. The test cases listed in Table I are carried out to investigate the effect of decoupling (including PCB stackup and capacitors) on SSN and EMC.
In test case 1, the prototype PCB consists of four signal layers and one ground layer. There are sixteen 0.1µF decoupling capacitors tied to the +1.8V power pins of FPGA on the PCB for this test case. Meanwhile in test case 2, the prototype PCB consists of four signal layers and three ground layers. There are twenty five 0.1µF decoupling capacitors tied to the +1.8V power pins of FPGA on the PCB for this test case.
Table I. Test cases to study effect of PCB decoupling on SSN and EMC
With reference to PDN impedance plot (post-layout power integrity analysis performed using Mentor Graphic Hyperlynx) in Fig. 1, the power net in test case 2 has lower impedance across the wideband range due to its improved decoupling condition compared to test case 1. The 0.1µF capacitors contribute in frequency from low to mid-band (<400MHz). On the other hand, plane capacitance due to ground layers contributes in frequency beyond 400MHz. A lower PDN impedance is experienced by test case 2 due to its higher number of decoupling capacitors and ground layers compared to test case 1.
Fig. 1. Plot of PDN impedance
Subsequently, the power spectrum of the +1.8V (probed using spectrum analyzer through AC coupling) that spans from 30MHz to 1000MHz is compared for both test cases. Referring to case 2 indicated by spectrum in Fig 2b, the spur observed are mainly contributed by the harmonics of crystal oscillator (50MHz fundamental), DDR2 SDRAM (350MHz fundamental), ADC data bus (150MHz fundamental), and the ethernet (100MHz fundamental). The spur with the highest power occurs on the spectrum of test case 1, as shown in Fig 2a, due to poorer decoupling.
C.F. Yee has been working in Keysight's Electronic Measurement Group since 2006 with experience in embedded system HW design, multi-Gigabit backplane design, signal integrity, power integrity, EMI, and jitter/phase noise analysis.