New memory technologies force us to challenge past design assumptions. Read this introduction to FRAM, DDR SDRAM, and RDRAM before starting your next project.
Configuration data goes into EEPROM; variables and structures into SRAM. The DRAM we use is the cheapest available for the speed we need. For a long time, we've had the luxury of designing without having to question these assumptions. Well, those days are gone. New technologies are here and they are forcing us to take a fresh look at our memory world.
FRAM, DDR SDRAM, and Rambus DRAM (RDRAM) already have come into view along the memory horizon. SDRAM sailed in several years ago. Look for FRAM on 8- and 16-bit catamarans, while DDR SDRAM and RDRAM grapple for control of the 64-bit supertankers. We'll look at each of them to see what they offer and how they challenge the existing technologies.
- RAM-Random access memory, meaning that each memory location can be accessed as easily and quickly as any other. In common usage, RAM has come to mean any quickly writeable, volatile memory.
- ROM-Read-only memory, meaning that once written, the memory cannot be modified. In common usage, ROM has come to mean nonvolatile memory that is cumbersome to write.
- DRAM-Dynamic RAM, dynamic because this memory must be periodically refreshed or the cells will discharge to a meaningless state.
- EPROM-Electrically programmable ROM, memory that is written to with a dedicated device and erased by exposure to ultraviolet light.
- EEPROM-Electrically erasable programmable ROM, electrically erasable instead of ultravioletly erasable like EPROM. It can be written to by a microcontroller
- Flash-Easily, but slowly, written nonvolatile memory.
- PROM-Programmable ROM, programmed once and only once; truly read-only memory.
- SRAM-Static RAM, static because once written, the data persists for as long as power is present.
- SDRAM-Synchronous DRAM, synchronous because the data is delivered according to a clock signal.
The underlying technology of FRAM has been around since 1921, but only recently has it been exploited. RAMTRON International, the first to successfully manufacture FRAM, was founded in 1984 to develop and license FRAM. All currently available FRAM products are manufactured by or licensed by RAMTRON.
FRAM offers the best of RAM and ROM; write times are fast and the memory can be used as nonvolatile storage. It has a mixture of existing memory features: the one-transistor cell of DRAM, the price of SRAM, and some of the persistence of flash. It seems a perfect combination, but it isn't. Due to the physical nature of the FRAM cell, there is a limit to the number of accesses it will tolerate before it loses its nonvolatility. More on the implications of that feature later.
FRAM takes its name from the ferro-electric crystal at the heart of the memory. This material might not be what you think it is. The “ferro” could lead you to believe that the material has something to do with magnetism-it doesn't. The “electric” suggests the memory is a storage of charge-it isn't.
Ferro-electric materials store state based upon the position of free atoms within the crystal. There are only two stable positions for the free atoms. One of those stable positions is used to hold logic 1, the other for logic 0. The nice thing about the crystal's behavior is that it requires no power to preserve state. That is how FRAM achieves nonvolatility. Turn off the power and your data will still be there for you a decade later.
Unfortunately, this isn't the entire story. The crystal can “wear out.” After enough reads, the memory is no longer nonvolatile. FRAM datasheets give 10 billion (1010) as the maximum number of reads. After this maximum number of reads is realized, the data will not persevere in the absence of power. That's not to say that all is lost. What remains is still perfectly useful RAM; it's just not nonvolatile anymore.
The present FRAM cell has two transistors. One holds the bit, the other its complement. The read-then-refresh method of data retrieval results in access times comparable to run-of-the-mill DRAM. You can buy FRAM with 70ns access times. Fast write times and nonvolatility-even less-than-ideal nonvolatility-make for a plum package, but how does it measure up to the standard memories?
FRAM vs. EEPROM
Every design requires memory that is ready at power-up. You have to be able to start somewhere. In the simplest designs this might merely encompass the program code itself, burned into PROM. More complex designs use a separate boot code section, isolated from the main program. Since this boot code is small, rarely modified, and has to be nonvolatile, EEPROM has been a good choice for its storage. The slow write times of EEPROM are tolerable since the boot code is usually only modified during development, then left alone.
FRAM must be considered as an alternative to EEPROM for storing boot code. It has the features that EEPROM offers, but in a faster package. However, before committing to FRAM, you've got to convince yourself that you are in absolutely no danger of hitting the 1010th read of the boot code. It's a bad thing if you miscalculate and the product dies because the boot code evaporated one night.
That said, FRAM can be a good match for boot code. This code probably is accessed only at start-up and I suspect that very few applications go through 10 billion starts in their lifetime.
Another common use of EEPROM is for storage of configuration data. These are personal preferences selected by the user that ought to be ready for him every time he turns on the device. The access frequency might be the same as boot code, but some care must be taken.
If you are using EEPROM with its unlimited number of reads, you can access the configuration data during runtime as often as you wish. You cannot do the same with FRAM, but handling the maximum-reads constraint needn't be a problem. Instead of worrying about hitting the 1010 ceiling, you could merely copy the data into another memory at start up. Maybe that memory is SRAM, but maybe it isn't. We shall see.
FRAM vs. SRAM
Runtime variable data in small applications goes into SRAM. We need fast write times so we pay the relatively high price for SRAM. Since we usually don't need too much, we accept the cost. Additionally, it's very easy to work with SRAM; it has none of the timing headaches of DRAM and none of the serial headaches of EEPROM. FRAM cannot challenge SRAM head to head. For the same price, SRAM is much faster. But viewed within the whole of the design, FRAM makes you think a little bit.
If you have an application that needs approximately 3KB of SRAM and a few hundred bytes for boot and configuration data, your set-up probably looks like that in Figure 1.
Suppose that this little application can get along just fine with 70ns access time for its variable memory. If that's the case, you can put one FRAM chip down and cover all your bases. This is shown in Figure 2.
The nonvolatility takes care of boot and configuration (assuming you've done your maximum-reads homework). The part of the FRAM that you use for the variable data is indeed nonvolatile, but this costs you nothing. And once it becomes volatile after enough accesses, so what? You haven't lost anything since you didn't need the nonvolatility there in the first place. All in all, it's an option worth considering.
As good as FRAM is for the memory needs examined so far, it's still far from being the ideal universal memory. Comparisons to DRAM and flash will show you why.
FRAM vs. DRAM
DRAM is the memory of choice when density and price are more important than speed. For example, DRAM is the perfect fit for visual display memory needs. There are lots of pixels to store, but retrieval time is not of the essence. And since there is no need to preserve the memory for the next startup, volatile RAM is just fine.
DRAM seems to be changing weekly and to thoroughly compare FRAM and DRAM, we should discuss the next generation of DRAM. While this makes the strongest case for DRAM, it would be overkill. Truth be told, DRAM doesn't need the extra help. If you need a lot of cheap memory, FRAM is simply not for you. Compare 20 cents per kilobyte of FRAM to 50 cents per megabyte of DRAM if you have any doubts.
FRAM vs. flash
Program memory is frequently flash memory nowadays. It's too easy to use and too cheap to be avoided.
Program memory has to be nonvolatile and relatively inexpensive. With the widespread adoption of flash, it is now taken for granted that the memory must also be easily changed. Yet, another characteristic of program memory is essential, but hardly considered: you must be able to read it forever. When FRAM enters the picture, this must be considered.
I did a quick calculation to see what kind of restrictions FRAM imposes. Suppose I have a loop that processes 100 bytes, one byte at a time, every 50ms. That being the case, the loop code will be read for the 10 billionth time after two months of continuous operation. If that loop has been stored in FRAM, it is gone with the next power down. When the makers of FRAM eliminate the maximum-number-of-reads restriction, it is going to be a formidable player in the memory games, but for now, flash vendors have little to worry about.
FRAM in production today already offers viable alternatives to existing memory technology. It is a perfect fit for the EEPROM niche and can offer an elegant way to consolidate SRAM and EEPROM needs in some applications. But until the maximum number of reads is eliminated, the coronation of FRAM as the universal memory is still a long way off.
DRAM, SDRAM, and the next generation
Analyzing the memory needs of your system is all about juggling the three balls of speed, size, and cost. Concentrate too closely on just one of them and you lose the other two. DRAM users must keep these three in the air as well as a fourth; they have to consider the control protocol for the memory.
By its nature, DRAM requires the manipulation and precise timing of several control lines. You can't choose your DRAM chip until you are sure you can control the memory. The designer has two choices: he can handle the control himself-with an ASIC or FPGA-or he can buy a chip dedicated to controlling the specific DRAM he is using. DRAM controllers were once stand-alone chips, but can now be found onboard high-end processors.
The applications we will examine will show how the control of the memory and the memory itself are inseparable. We'll begin with an introduction to three of the newest DRAMs.
Run-of-the-mill DRAM required approximately 60ns to access. Put this DRAM on a 4MHz bus and you have a good match. The bus only comes around every 250ns. Try to put that same DRAM on a 100MHz bus and you have a problem. Every 10ns, this bus comes around, so the controller waits six cycles to get at the memory it needs. Clearly, faster memory is needed.
Synchronous DRAM (SDRAM) solves the problem by guaranteeing data at a rated frequency. The SDRAM data is synchronized to the bus's clock. Although SDRAM imposes a set-up time and the possibility of wait states, it delivers a high percentage of data at the rated frequency. Tie 100MHz SDRAM to a 100MHz bus and you have a well-matched, very fast system.
Whereas standard DRAM is accessed on demand and then requires a wait until the memory is ready, SDRAM delivers memory on every cycle. The underlying mechanism involves two banks of memory that store the chip's data. While one bank is being precharged, the other is being read.
Double Data Rate (DDR) SDRAM earns its name from its ability to deliver double the data of comparable SDRAM. DDR is an evolution of SDRAM. It delivers data on both the rising and the falling edge of the clock signal, thereby doubling the output of an SDRAM tied to the same clock.
DDR SDRAM delivers twice the data at twice the price. SDRAM sells at $4 for 64Mbits, but the same amount of DDR SDRAM is quoted at $8. Presently, few companies are manufacturing DDR SDRAM. Although the chips can be manufactured with acceptable yields, DDR's ability to gain a foothold in the market has been uncertain. From the beginning of its Pentium 4 development, Intel had locked out DDR SDRAM from its plans. The company retreated from that decision in late July 2000; nevertheless, anyone considering the step to DDR SDRAM has had to consider not only the technology itself and the price forecast, but whether manufacturers would be enticed to produce it.
DDR SDRAM's chief competition is from Rambus DRAM (also referred to as RDRAM). RDRAM is an entirely different animal. It is a system-wide interface, relying on its own protocol. It is very fast, with a top speed of 833MHz. Manufacturers have had a difficult time producing it in marketable quantities, thus keeping the price high. Additionally, any use of Rambus requires the payment of a licensing fee which also adds to the bottom line.
Now that we have a feel for the memories, we can look at three places they are used: in mid-level applications, in high-speed networks, and with the latest Intel chip in desktop PCs. As we did with FRAM, we'll begin by comparing them to the existing technology.
The new DRAMs and EDO DRAM
If you have seen a child with his touch-screen computer, pushing icons to create vocalizations, then you have almost certainly seen one of my company's augmentative communication devices. They are not quite as sophisticated inside as the PC on your desktop, but they are definitely slicker than your smart toaster.
The device wants to make it easy for the child to get her idea out as quickly as possible. To realize this, the device does a lot of prediction. If the child begins a sentence with “I want a blue…” the machine is ready with anything she has ever described as blue. Maintaining the data structures to implement the prediction brings us to DRAM.
Until recently Extended Data Out (EDO) DRAM has been the DRAM of choice. It reaches speeds of 83MHz, but has wait sequences inherent in its design. SDRAM is coming on so strong that EDO's days are numbered and it is not recommended for new designs. Since EDO is the DRAM used in our current line of devices, we had to look to the newer DRAMs for the next generation of our products.
The designers considered SDRAM, DDR SDRAM, and Rambus DRAM for the run-time memory they would need. The design team's analysis illustrates how the memories compare in a real application.
As Jeff Holt, the lead hardware designer, explained it, the new device requires memory delivered at 100MHz. This would be fast enough to guarantee that the predictions would appear in the blink of an eye. An analysis of the data structures put their RAM requirement at around 32MB. A lot of memory in a small, relatively inexpensive product led them to conclude that some sort of DRAM was certainly going to be the choice.
SDRAM rated at both 100MHz and 133MHz is available off the shelf. That puts the DDR SDRAM at 200MHz and 266MHz. As mentioned above, Rambus DRAM is significantly faster than that; you can buy 400MHz and 800MHz RDRAM. Being good designers, my team doesn't over design, thus SDRAM was deemed the best fit. Furthermore, the processor they had chosen, the Intel StrongARM, provides the control signals needed to use SDRAM. Unfortunately, it supports neither DDR SDRAM nor Rambus.
Given that its speed was acceptably fast, its price was the lowest of the three, and our processor required no extra control chip, the choice of SDRAM was a no-brainer.
One of the assumptions stated at the beginning of the article was that we choose the cheapest DRAM for the speed we need. This application did indeed end up with the cheapest DRAM it could find for the speed it needed, but it also had the full range of DRAMs to consider. Not all designers have such a wealth of choices.
Designers planning to use the Pentium 4 this year have one less thing to worry about: they don't have to choose which memory to use. Intel made that choice for them years ago when they wedded this chip to Rambus technology. Whether you need all of that speed or not, you've got it. Anyone wishing to hook the chip up to SDRAM or DDR SDRAM must wait until next year. (Both Via Technologies and Acer Laboratories have promised chip sets that will connect both types of SDRAM to the latest Pentium.)
A common high-end application is in network development. Our distributors inform me that they are selling a lot of 400MHz Rambus to the designers of these systems. The price is high, in the $700 per 256Mbits range, but these folks are willing to pay it. The 133MHz SDRAM doesn't pass muster. They feel they need the speed and the cheapest they can find is in fact the only one available. DDR SDRAM speeds are sure to increase and then they will have a much cheaper choice. The DRAM rule of thumb still holds true.
Change in the memory world is as brisk as the world at large. FRAM has exciting possibilities to offer now and in the future for the imaginative designer. For explorers at the frontier of DRAM technology, the bravest will investigate all possible trails, then elegantly devise fast and cheap solutions. The horizon has never looked wider, nor brighter.
Dan Sweeney holds bachelor's degrees in mathematics and computer engineering. He is presently designing a network for medical devices for DynaVox Systems. He thanks Paul Miller, Andy Alexander, Jeff Holt, Mick Daum, Deneen Pavlik, Greg Powanda, Lisa Orlandi and Mike Alwais for their assistance; and Valerie for her patient editing. Contact him by e-mail at .
1. Available in the next generation of FRAM.
2. It isn't the read itself that wears out the crystal. The wear is caused by the write that must follow each read, since the read process destroys the data.
3. SRAM was selling at around 25 cents per kilobyte in mid-January.
4. After a small startup penalty.
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