To NAND or NOR. That is the question. Different applications and functions should be handled with different types of flash memory.
In their search for the perfect “universal memory,” designers of embedded systems are like characters from the play Waiting for Godot . They're waiting for an off-stage character, “Godot,” to come on stage, meanwhile speculating which of the current or new characters appearing on stage are Godot.
From it's inception in the 1970s, the embedded systems industry as we know it as always been waiting for an off-stage semiconductor-based character named “universal memory” to come along and replace the memory hierarchy inherited from mainframes, minicomputers, and desktop computers: nonvolatile hard disk drives for long term mass storage and backup, dynamic RAM for local fast memory access, and SRAM and ROM for extremely fast access and code storage.
This desire has been heightened and intensified as computing as become more embedded, mobile, and portable and candidates for the role of “universal memory” have come on stage. Some–such as EEPROMS, EPROMs, UV-EPROMs, ferroelectric RAMs, and various pseudo-RAM combinations–have been turned down. Others such as magnetic RAM are being considered, but are in doubt for a number of economic and technical reasons.
However, some of the current characters on the stage–particularly the various flavors of NAND and NOR flash EPROMs–are being touted by their vendors as that offstage character “universal memory,” or at least a relative and “close personal friend” including OneNAND, OrNAND, iNAND, GBNAND, moviNAND, ManagedNAND and NANDrive. Giving the diversity of actors trying out for the role, choosing the right memory subsystem is much more complicated now, especially if you're adding more multimedia functions to mobile and embedded systems while shrinking physical size and reducing overall system cost. Not only could the code and data storage needs have increased in these systems, but you've got to do it all more reliably with less of everything.
Flash memory is the most practical solution, but knowing which type of flash fits best in a system is the key. Is NAND, NOR, managed NAND, or some hybrid the best choice?
The use of NAND flash, an inexpensive and high-density nonvolatile memory requiring defect management, to satisfy these growing code and data storage needs makes the memory subsystem even more complex. Add to that the need to support different memory types, interfaces, vendors, and vendor-specific features, and the memory subsystem even more complex.
A completely managed memory subsystem solution can be designed that uses an industry-standard RAM (PSRAM or SDR/DDR SDRAM) interface. This managed memory subsystem would provide seamless integration with the host chipset/processor and eliminate the need for the host system to manage the complexity and deficiency of built-in memory devices.
Unlike NAND flash, NOR flash is one of the oldest and the most widely used memory types in current embedded systems. It's used for both code and data storage. Its main advantage is that the code is executed directly (execute-in-place) from the NOR flash memory. Also, NOR flash can directly interface with the host processor, which enables easy design-in and fast time-to-market.
With the increased deployment of multimedia functions in embedded systems, the need for code and data storage is also increasing. For these applications, using higher density NOR flash for code and data storage becomes more expensive when compared with alternative solutions like NAND flash. In addition, the highest density NOR flash available today is 1 Gbit. Moreover, multimedia data storage requires both high read and write performance. As a result, system designers have turned to NAND flash for storing multimedia files as well as application code in many embedded applications, including high-end cell phones.
NAND for code & Data storage
NAND flash is well suited for applications that require large code storage (such as operating system and applications) and large data storage because NAND flash is inexpensive and is also available in high densities (up to 16 Gbits in one die). Unlike NOR, NAND flash doesn't support execute in place (XIP) or random access. As a result, some systems that use NAND flash need a low-density NOR flash just for system boot-up and BIOS code execution. In other systems, a NAND flash controller, or an embedded boot ROM in the host processor, can provide the boot function. After system boot-up, the NAND-based systems use either code shadowing or demand paging for code execution. In the case of code shadowing, the entire operating system and applications are copied from the NAND flash into the system RAM, and in demand paging, a portion of the operating system and applications are copied into the system RAM as needed, where such code is then executed.
Though NAND flash is inexpensive and available in higher densities than NOR, NAND is less reliable and requires defect management, including error detection and correction, and wear-leveling to make it usable for many applications. These NAND flash management functions require complicated hardware and software. Figure 1 shows a system where the host chip set interfaces with standalone NAND flash. In this system, the defect management functions must be performed by the host chip set. Running such flash management functions on the host requires some software development and it also uses some of the host's CPU and memory resources, leading to a reduction in overall system performance.
As NAND flash vendors are moving to smaller process geometries, the ECC (error correction code) requirement for single-level cell (SLC) NAND flash has increased from 1 to 4 bits per 512-byte sector, and for multi-level cell (MLC) NAND flash, it's increased from 4 to 8 bits per 512-byte sector. The page size has increased from 512 to 4,096 bytes. The endurance for some of the smaller geometry SLC NAND flash has changed from 100,000 to 50,000 cycles, and for MLC NAND flash it has changed from 10,000 to 5,000 cycles (and 3,000 cycles in some cases). To reduce the number of discrete components in the system, many chip set vendors have started integrating a NAND flash controller in their chip set, which can directly interface with standalone NAND flash. However, because of the long design cycle of a chip set, it's difficult for the chip set vendors to track the ever changing NAND flash technologies. Therefore, the functionality of an embedded NAND flash controller in the chip set will always lag the NAND flash technologies.
A few solutions are similar to standard NAND flash, but offer improved performance and functionality. For example, OneNAND is a variation of NAND flash that combines RAM and standalone SLC NAND flash in one device to provide boot function and faster read access. OneNAND requires 1-bit ECC for each 512-byte sector and requires NAND flash management functions implemented either in the host chip set or in a separate standalone controller.
On the other hand, OrNAND combines MirrorBit NOR with a NAND flash interface, which offers faster write time than its predecessor NOR devices. OrNAND also requires 1-bit ECC implemented either in the host chip set or in a separate standalone controller to ensure reliable system boot-up. Moreover, the maximum density currently supported by OrNAND is only 1 Gbit, which is less than the maximum density of currently available NAND flash.
Managed NAND for data
Due to the limitations of the embedded NAND controllers, many system designers are looking at managed NAND solutions. Several vendors have come up with managed NAND memory products that alleviate the complexities of a conventional memory subsystem in embedded applications. These managed NAND memory products, including iNAND, GBNAND, moviNAND, Managed NAND, and NANDrive, are used mainly for data storage. They reduce system complexity by effectively managing the built-in NAND flash with a NAND controller and flash file system (FFS) integrated into the same device as shown in Figure 2 . These products use a standard interface such as Secure Digital (SD), MultiMediaCard (MMC), or Advanced Technology Attachment (ATA) for easier integration. For example, iNAND and GBNAND offer the SD interface, moviNAND and Managed NAND offer the MMC interface, and NANDrive offers the ATA interface. These products don't offer XIP access and as a result, systems that use them may need a NOR flash for the boot function.
Using a managed NAND device eliminates the need for a complex NAND management function on the host. As a result, the chip-set vendors needn't worry about keeping up with the evolving NAND technologies, thus enabling vendors to focus more on their core competencies.
Managed NAND hybrid boots
Because managed NAND flash doesn't provide boot capability, system designers still must use a higher cost NOR flash device for boot-up. However, hybrid products, including mDOC H3, are now available. These hybrids use RAM and managed NAND in a one device, as depicted in Figure 3 , to simplify the conventional memory subsystem.
Hybrid products solve the boot issue associated with the managed NAND. They can boot directly from the NAND flash, eliminating the need for a higher cost boot NOR flash device, which may reduce the overall system cost. Managed NAND hybrids also help to reduce component count and save board space, which makes them suitable for space-sensitive applications like cell phones. These solutions are available in higher densities because they use NAND flash for nonvolatile storage.
On the down side, NAND hybrids have a longer boot time because they must copy the boot code from the NAND into the boot RAM after power-on. Also, NAND hybrids are complex, difficult to integrate, and require an advanced operating system that supports demand paging on the host.
mDOC H3 uses a NOR-type bus to interface with the host processor and offers faster read performance than NAND flash and faster write performance than NOR. Due to the faster write performance, these devices are suited for storing multimedia.
Using a managed NAND or even a managed NAND hybrid with boot capability doesn't drastically reduce the memory subsystem's overall complexity. The system designers must still manage the complexity associated with different memory types, interfaces, vendors, vendor-specific features, and so forth. These types of memory subsystems require many components, more pins, and complex hardware and software development, resulting in increased system cost, board space, development time, and power consumption. At the same time, they increase the complexity of the external memory controller in the host processor. Therefore, these hybrids are less than complete. Today's systems need an easy-to-use, single-standard bus, completely managed memory subsystem for code and data storage and system RAM, all in one device.
What system designers need is a complete memory subsystem that offers hundreds of megabytes of XIP code storage and also satisfies the growing data-storage needs of today's multimedia applications. The solution should blend the key benefits of NOR (fast read), NAND (lower cost and higher density), and RAM (simple bus operation). This solution also must be easy to use, easy to design in, and completely managed. Thus, it requires minimal or no additional hardware or software development, offers a standard interface for seamless integration with the host chip set/processor without any glue logic, and makes memory subsystem access as simple and easy as an SRAM.
The built-in controller in this memory subsystem solution must implement ECC, bad block management, and wear-leveling to manage the defects in the built-in NAND flash. The controller must also manage the complexity and deficiency of all the built-in memories (NOR, NAND, and RAM) to off-load the host system from handling these complicated management functions.
Furthermore, this solution must address the total system cost by reducing the material, development, and manufacturing costs. In addition, it must address the time-to-market needs of system designers working on mobile and consumer electronic devices by offering a solution that's easy to integrate and is scaleable for future products.
Next generation subsystem
Managed memory subsystem products are available today that offer all the features and benefits mentioned. For example, one such configuration shown in Figure 4 consists of a memory controller with built-in boot NOR flash, NAND flash and RAM, all in one package. Using the RAM cache in front of the NAND flash, the controller handles on-demand paging and other memory management functions. In addition, the RAM cache renders the memory subsystem addressable linearly, and as simple as an SRAM.
The RAM block is divided into two host-accessible, user-configured partitions: a cache partition for Pseudo-NOR (PNOR) and a system RAM partition for the host. The NAND block is used as nonvolatile storage for the PNOR area and the memory-mapped ATA NAND disk area. The configurable PNOR block emulates the NOR function by using RAM cache and NAND flash. Because NAND is used as the main nonvolatile storage media, this solution provides large XIP code storage that can effectively replace the traditional higher cost, high-density NOR flash. By using the industry standard ATA data-storage protocol on the standard RAM (PSRAM or SDR/DDR SDRAM) bus, this solution provides large ATA-like data storage for the growing multimedia applications. In addition, the RAM cache in the PNOR block also helps to extend the endurance and reliability of the code and data storage area by minimizing direct read/write access to the NAND flash.
Because it's offered in a small-footprint package, this managed memory subsystem may simplify the host interface, reduce system complexity, shorten design time, reduce overall system cost, and improve quality and reliability. Other benefits include the user-configurable XIP PNOR area; robust hardware error detection and correction for MLC and SLC NAND; and scalability to higher densities. With no complicated software and hardware development required, this type of managed memory subsystem could be the Godot we're all waiting for.
Vijay Devadiga is currently a senior staff product marketing engineer at Silicon Storage Technology Inc. in the NAND and Smartcard Module Business. In this role, he is responsible for product marketing of the company's All-in-OneMemory product line. He can be reached at email@example.com.