Energy harvesting demands full-spectrum microcontroller efficiency

Energy harvesting provides the key to a new generation of devices that allow intelligent sensors to be deployed in a far wider range of situations than previously possible. Such sensors allow continuous condition monitoring in applications as disparate as industrial motors and body-worn sensors for long-term physical health measurement.

Although these systems could use battery power to avoid the need to connect the sensors to mains power, batteries will need to be replaced or recharged during their lifetime. Once placed around a large motor or turbine, for example, it can be difficult to gain access to replace them. The advantage of many of these applications however is that they can be harnessed for energy themselves.

The vibration of an industrial motors can be used, with an appropriate seismic mass and converter, to generate energy for the system that monitors it. Similarly, for body-worn sensors, vibration and thermal energy capture can trickle charge into a capacitor that can then be used to power a sensor. (fig 1)

Figure 1: Power density of Energy Harvesting Methods. (Source: The Journal of Technology Studies) 

Although these systems provide mechanisms for capturing energy, they rarely generate the levels of power that designers are accustomed to working with on battery-fed systems. Therefore, it is vital to have a system engineered to consume the minimum power wherever possible.

A key target for reducing power in the logic circuitry is that of the operating voltage. In CMOS circuitry, there is a quadratic relationship between voltage and power consumption, as shown in the equation P = CV2 f, where C is the circuit capacitance, f is the switching frequency and V is the voltage applied. Clearly, reducing the voltage offers the greatest potential for reducing power consumption. Near- and sub-threshold operation of transistors offers a unique approach to reducing the operating voltage in microcontrollers and other logic circuits to levels that are well below those required by standard logic.

The principle behind near- and sub-threshold operation is that the threshold voltage at which the device would normally be considered to be switched “on” need not be treated as a required target for logic and analogue circuits. Logic transistors have traditionally been designed to pass high levels of current when saturated in order to charge the capacitive paths that follow each gate. However, it is possible to charge these circuit paths without switching the transistor into full saturation and instead allow current to trickle through more slowly. This has the consequence of causing logic to switch state more slowly but in typical sensor applications, there is no need to switch at the highest possible speed.

However, as threshold voltages are driven lower, there is also an exponential increase in the transistor leakage currents (fig 2)

Figure 2. (Source: Ambiq)

As the voltage falls even further into the deep sub-threshold realm, the proportion of energy lost through leakage will dominate, which places a secondary limit, on top of performance considerations, as to how far the supply voltage can be lowered. (fig 3)

Figure 3. (Source: Ambiq)

 A critical issue for designers of sub-threshold circuitry is process variation and its effects as the supply voltage approaches that of the threshold. Key to the effective design of sub-threshold circuitry are mechanisms to reduce the effects of this variation, such as adaptive circuitry that is specifically designed to overcome this variability. Development over many years at the University of Michigan and Ambiq Micro has led to many sub-threshold innovations such as this. The entire design flow must also be reengineered in order to effectively take advantage of this technology – from the standard cell libraries used to implement sub-threshold logic circuits all the way through to test strategies needed to test nanoamps and picoamps of current. Only with this level of investment is it possible to maximise the power-saving benefits of sub-threshold design.

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Although sub-threshold operation takes maximum advantage of the quadratic relationship between voltage and power consumption, it is not always the most appropriate transistor operation regime to choose. Because of the performance impact of sub-threshold operation, it can be beneficial on certain circuitry to use higher voltages – in the near-threshold or even the traditional super-threshold regime. Memory blocks, for example, do not always benefit from ultralow-voltage operation when being accessed.

In designing a power-efficient microcontroller, it is important to analyse at a circuit level the tradeoffs between voltage, power and performance. This work has been performed extensively on the Ambiq sub-threshold power optimised technology (SPOT) platform that lies at the core of the Apollo series of microcontrollers.

Although circuit-level design choices will play a role in optimising energy-harvesting IoT applications for power, system-level decisions have a major impact on overall energy consumption. A vital step is to minimise unnecessary activity, typically achieved through the intelligent application of sleep modes. Further enhancements can be made by favouring processor architectures that maximise the amount of work performed on each clock cycle.

Microcontrollers typically have more than one low-power sleep mode, which may range from a light sleep in which local memory and most peripherals remain powered up but the CPU core itself is idle through to a deep-sleep mode where most functions have been disabled and powered down. As fewer and fewer peripherals and core functions remain enabled, the energy savings increase. But there are key design tradeoffs.

Typically, an IoT sensor node will need to monitor the environment around it and react when system conditions change. Key to optimising a low-power embedded system, particularly one that relies on intermittent sources of power in the case of systems that use energy harvesting, is to find the lowest-power sleep mode that provides an adequate response to real-time events.

The lowest-energy sleep mode of a microcontroller in practical systems is typically that in which a real-time clock takes care of basic housekeeping functions and wakes the system periodically to check for activity. For example, a system may wake every second to check for changes in external conditions and move to fully wake the processor core if software needs to process the inputs. But this polling-based approach can be wasteful in systems where alert conditions are comparatively rare and not evenly spaced.

Faster responses to random interrupts can be ensured by having the system use a higher-energy sleep state to process I/O and quickly wake the processor core if thresholds are exceeded, but these modes may drain the energy reservoir leaving insufficient power for the processor to respond. However, it is possible to combine the best aspects of the deep-sleep mode and still provide the benefits of responsiveness to key inputs.

There are ultra-low energy real-time clock designs that can check for external issues, such as issues raised by hardware interrupts or changes in input voltage sensed by a comparator. When an external event is detected, the system can move to a waking state quickly without incurring the power penalties of implementing a polling strategy and maximising the period of time that the system spends in deep sleep.

When processing software, it is important to ensure that the maximum amount of work per clock cycle can be achieved. Many IoT sensor applications call for the use of signal processing algorithms to detect issues and pre-process data before it is relayed to the user and/or the cloud. This leads not only to the use of 32-bit processor architectures rather than 8-bit, as they handle mathematical operations using fewer cycles, but with architectures that provide full support for both fixed- and floating-point signal-processing instructions. Hardware support for floating-point arithmetic ensures that algorithms can be executed in far fewer cycles thus allowing the core to quickly return to a more energy-efficient sleep state with further reduces the overall system-level power. This combination of requirements leads to the selection of processors such as the ARM Cortex-M4F, as employed by the Ambiq Apollo family.

Thanks to improvements in energy efficiency from the system level down to low-level circuit operation that pushes voltage control to its limits, energy harvesting is becoming a practical option for an increasingly wide range of sensor-oriented designs for the internet of things.

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