Cadence Design Systems has released version 9.1 of the company's Encounter Digital Implementation (EDI). It's a complete and integrated digital design, implementation, and verification environment for the development of large-scale, complex SoCs. The expanded capabilities in EDI System 9.1 improves designer productivity in developing advanced low power and mixed-signal SoCs at leading-edge process nodes, such as 32 and 28 nm, with hundreds of millions of gates, including hundreds of IP elements and embedded processors.
By combining automatic floor-plan synthesis, unique data abstraction modeling, and new concurrent macro- and standard cell placement, all driven by fully the embedded signoff analysis capabilities of EDI System, users can quickly find and implement the optimal physical architecture of a chip. Design exploration does this by automatically and concurrently examining thousands of combinations of design variables, option settings, floor-plan architectures, and physical implementation approaches in parallel. This exhaustive examination lets users explore the range of design possibilities, and deliver smaller, faster, higher functioning chips, while accelerating design schedules.
EDI System improves designer productivity by broadening its integrated suite of native signoff capabilities. Building on its existing foundry certified power, timing, and signal integrity (SI) signoff capabilities, EDI System 9.1 adds silicon-accurate extraction and design-for-manufacturing (DFM) analyses to complete the picture.
The integrated, turbo QRC extraction capability provides fast in-design, incremental signoff extraction and drives fast and convergent design closure for physical and electrical design requirements. The integrated DFM capability, turbo Litho Physical Analyzer, brings built-in litho pattern intelligence and filtering to the interconnect routing phase, enabling automatic detection, prevention, and correction of potential litho hotspots before they happen.